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HC705JB2GRS/h rev 1.1 ? motorola, inc., 1998 68hc705jb2 specification (general release) august 28, 1998 consumer systems group semiconductor products sector motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part.

table of contents section title page august 28, 1998 general release specification mc68hc705jb2 motorola rev 1.1 i section 1 general description 1.1 features ...................................................................................................... 1-1 1.2 mask options.............................................................................................. 1-2 1.3 mcu structure.......................................................................................... 1-3 1.4 functional pin descriptions ............................................................... 1-4 1.4.1 vdd, vss .................................................................................................... 1-4 1.4.2 osc1, osc2 ............................................................................................... 1-4 1.4.3 reset ......................................................................................................... 1-6 1.4.4 irq/vpp ...................................................................................................... 1-6 1.4.5 pa0-pa7 ...................................................................................................... 1-7 1.4.6 pb0-pb2 ...................................................................................................... 1-7 1.4.7 d+, d ......................................................................................................... 1-7 1.4.8 3.3v ............................................................................................................. 1-7 section 2 memory 2.1 memory map ................................................................................................ 2-1 2.2 i/o and control registers ................................................................... 2-2 2.3 ram ................................................................................................................. 2-3 2.4 eprom ............................................................................................................ 2-3 2.5 bootloader rom....................................................................................... 2-3 section 3 central processing unit 3.1 registers .................................................................................................... 3-1 3.2 accumulator (a)........................................................................................ 3-2 3.3 index register (x) ..................................................................................... 3-2 3.4 stack pointer (sp) .................................................................................... 3-2 3.5 program counter (pc) ........................................................................... 3-3 3.6 condition code register (ccr) ........................................................... 3-3 3.6.1 half carry bit (h-bit) .................................................................................... 3-3 3.6.2 interrupt mask (i-bit) .................................................................................... 3-3 3.6.3 negative bit (n-bit) ...................................................................................... 3-3 3.6.4 zero bit (z-bit) ............................................................................................. 3-4 3.6.5 carry/borrow bit (c-bit) ............................................................................... 3-4 section 4 interrupts 4.1 cpu interrupt processing ................................................................... 4-1 4.2 reset interrupt sequence .................................................................. 4-2 4.3 software interrupt (swi) ..................................................................... 4-4 4.4 hardware interrupts ............................................................................ 4-4
general release specification august 28, 1998 motorola mc68hc705jb2 ii rev 1.1 table of contents section title page 4.4.1 external interrupt (irq) ............................................................................... 4-4 4.4.2 irq control/status register (icsr) $0a ..................................................... 4-5 4.4.3 optional external interrupts (pa0-pa3)....................................................... 4-6 4.4.4 timer1 interrupt (timer1)........................................................................... 4-7 4.4.5 usb interrupt (usb) .................................................................................... 4-7 4.4.6 mft interrupt (mft) .................................................................................... 4-7 section 5 resets 5.1 external reset (reset).......................................................................... 5-2 5.2 internal resets ........................................................................................ 5-2 5.2.1 power-on reset (por) ............................................................................... 5-2 5.2.2 usb reset ................................................................................................... 5-2 5.2.3 illegal address reset (iladr)..................................................................... 5-3 5.2.4 low voltage reset (lvr) ............................................................................ 5-3 section 6 low power modes 6.1 stop mode.................................................................................................... 6-1 6.2 wait mode .................................................................................................... 6-1 6.3 data-retention mode.............................................................................. 6-3 section 7 input/output ports 7.1 port a............................................................................................................ 7-2 7.1.1 port a data register.................................................................................... 7-2 7.1.2 port a data direction register..................................................................... 7-2 7.1.3 port a pulldown register............................................................................. 7-3 7.1.4 port a drive capability................................................................................. 7-3 7.1.5 port a i/o pin interrupts............................................................................... 7-3 7.2 port b............................................................................................................ 7-4 7.2.1 port b data register.................................................................................... 7-4 7.2.2 port b data direction register..................................................................... 7-5 7.2.3 slow output falling-edge transition ........................................................... 7-5 7.2.4 port b pulldown/pullup register.................................................................. 7-5 7.3 i/o port programming ............................................................................ 7-6 7.3.1 pin data direction........................................................................................ 7-6 7.3.2 output pin.................................................................................................... 7-6 7.3.3 input pin....................................................................................................... 7-6 7.3.4 i/o pin transitions ....................................................................................... 7-7 7.3.5 i/o pin truth tables..................................................................................... 7-7
table of contents section title page august 28, 1998 general release specification mc68hc705jb2 motorola rev 1.1 iii section 8 multi-function timer 8.1 timer registers ........................................................................................ 8-2 8.1.1 timer counter register (tcnt) $09 ........................................................... 8-2 8.1.2 timer control/status register (tcsr) $08 ................................................. 8-3 8.2 operation during stop mode .............................................................. 8-4 section 9 programmable timer 9.1 timer registers (tmrh, tmrl)............................................................... 9-2 9.2 alternate counter registers (acrh, acrl) .................................. 9-3 9.3 input capture registers ...................................................................... 9-5 9.4 output compare registers ................................................................. 9-6 9.5 timer control register (tcr) ............................................................. 9-8 9.6 timer status register (tsr)................................................................. 9-9 9.7 timer operation during wait mode................................................. 9-10 9.8 timer operation during stop mode ................................................ 9-10 section 10 universal serial bus module 10.1 features .................................................................................................... 10-1 10.2 overview.................................................................................................... 10-2 10.2.1 usb protocol ............................................................................................. 10-3 10.2.2 reset signaling.......................................................................................... 10-8 10.2.3 suspend..................................................................................................... 10-9 10.2.4 resume after suspend.............................................................................. 10-9 10.2.5 low speed device................................................................................... 10-10 10.3 clock requirements........................................................................... 10-11 10.4 hardware description....................................................................... 10-11 10.4.1 voltage regulator .................................................................................... 10-11 10.4.2 usb transceiver...................................................................................... 10-12 10.4.3 receiver characteristics.......................................................................... 10-13 10.4.4 usb control logic ................................................................................... 10-15 10.5 i/o register description ................................................................... 10-18 10.5.1 usb address register (uaddr)............................................................. 10-19 10.5.2 usb interrupt register 0 (uir0) .............................................................. 10-19 10.5.3 usb interrupt register 1 (uir1) .............................................................. 10-20 10.5.4 usb control register 0 (ucr0) .............................................................. 10-22 10.5.5 usb control register 1 (ucr1) .............................................................. 10-23 10.5.6 usb control register 2 (ucr2) .............................................................. 10-24 10.5.7 usb status register (usr)..................................................................... 10-25 10.5.8 usb endpoint 0 data registers (ue0d0-ue0d7)................................... 10-26 10.5.9 usb endpoint 1/endpoint 2 data registers (ue1d0-ue1d7) ................ 10-26
general release specification august 28, 1998 motorola mc68hc705jb2 iv rev 1.1 table of contents section title page 10.6 usb interrupts...................................................................................... 10-27 10.6.1 usb end of transaction interrupt............................................................ 10-27 10.6.2 resume interrupt ..................................................................................... 10-28 10.6.3 end of packet interrupt ............................................................................ 10-28 section 11 eprom 11.1 eprom .......................................................................................................... 11-1 11.2 bootloader .............................................................................................. 11-1 11.2.1 bootloader mode ....................................................................................... 11-1 11.3 eprom programming ............................................................................. 11-2 11.3.1 eprom program control register (pcr)................................................. 11-2 11.3.2 programming sequence ............................................................................ 11-2 11.4 mask option register (mor), $01ff................................................... 11-4 section 12 instruction set 12.1 addressing modes ................................................................................. 12-1 12.1.1 inherent...................................................................................................... 12-1 12.1.2 immediate .................................................................................................. 12-1 12.1.3 direct ......................................................................................................... 12-2 12.1.4 extended.................................................................................................... 12-2 12.1.5 indexed, no offset..................................................................................... 12-2 12.1.6 indexed, 8-bit offset .................................................................................. 12-2 12.1.7 indexed, 16-bit offset ................................................................................ 12-3 12.1.8 relative...................................................................................................... 12-3 12.1.9 instruction types ....................................................................................... 12-3 12.1.10 register/memory instructions .................................................................... 12-4 12.1.11 read-modify-write instructions ................................................................. 12-5 12.1.12 jump/branch instructions .......................................................................... 12-5 12.1.13 bit manipulation instructions...................................................................... 12-7 12.1.14 control instructions.................................................................................... 12-7 12.1.15 instruction set summary ........................................................................... 12-8 section 13 electrical specifications 13.1 maximum ratings..................................................................................... 13-1 13.2 thermal characteristics ................................................................... 13-1 13.3 dc electrical characteristics........................................................ 13-2 13.4 usb dc electrical characteristics ............................................... 13-3 13.5 usb low speed source electrical characteristics............... 13-4 13.6 control timing ........................................................................................ 13-5 13.7 eprom programming specifications .............................................. 13-5
table of contents section title page august 28, 1998 general release specification mc68hc705jb2 motorola rev 1.1 v section 14 mechanical specifications 14.1 20-pin plastic dual-in-line package (pdip) ..................................... 14-1 14.2 20-pin surface-mount small outline package (soic) ............... 14-2
general release specification august 28, 1998 motorola mc68hc705jb2 vi rev 1.1 table of contents section title page
list of figures figure title page august 28, 1998 general release specification mc68hc705jb2 motorola rev 1.1 vii 1-1 mc68hc705jb2 block diagram...................................................................... 1-3 1-2 pin assignments for 20-pin package............................................................... 1-4 1-3 oscillator connections ..................................................................................... 1-5 2-1 mc68hc705jb2 memory map ........................................................................ 2-1 2-2 i/o registers .................................................................................................... 2-2 2-3 i/o registers $0000-$000f.............................................................................. 2-4 2-4 i/o registers $0010-$001f.............................................................................. 2-5 2-5 i/o registers $0020-$003f.............................................................................. 2-6 2-6 mask option register $01ff ........................................................................... 2-6 3-1 mc68hc05 programming model ..................................................................... 3-1 4-1 interrupt processing flowchart ........................................................................ 4-3 4-2 external interrupt (irq) logic .......................................................................... 4-4 4-3 irq control and status register (icsr)......................................................... 4-5 5-1 reset block diagram ....................................................................................... 5-1 6-1 stop/wait flowchart..................................................................................... 6-2 7-1 port a i/o circuitry ........................................................................................... 7-2 7-2 port b i/o circuitry ........................................................................................... 7-4 7-3 port b data direction register ......................................................................... 7-5 8-1 multi-function timer block diagram ................................................................ 8-1 8-2 timer counter register.................................................................................... 8-2 8-3 timer control/status register (tcsr)............................................................. 8-3 9-1 programmable timer block diagram ............................................................... 9-1 9-2 programmable timer counter block diagram ................................................. 9-2 9-3 programmable timer counter registers (tmrh, tmrl)................................ 9-3 9-4 alternate counter block diagram..................................................................... 9-4 9-5 alternate counter registers (acrh, acrl).................................................... 9-4 9-6 timer input capture block diagram................................................................. 9-5 9-7 input capture registers (icrh, icrl)............................................................. 9-6 9-8 timer output compare block diagram ............................................................ 9-7 9-9 output compare registers (ocrh, ocrl) .................................................... 9-7 9-10 timer control register (tcr) .......................................................................... 9-8 9-11 timer status registers (tsr) .......................................................................... 9-9 10-1 usb block diagram ....................................................................................... 10-2 10-2 supported transaction types per endpoint................................................... 10-3 10-3 supported usb packet types ....................................................................... 10-4 10-4 sync pattern................................................................................................... 10-4 10-5 sop, sync signaling and voltage levels ...................................................... 10-5 10-6 crc block diagram for address and endpoint fields................................... 10-6 10-7 crc block diagram for data packets ........................................................... 10-7 10-8 eop transaction voltage levels ................................................................... 10-8 10-9 eop width timing.......................................................................................... 10-8 10-10 external low speed device configuration................................................... 10-10 10-11 regulator electrical connections ................................................................. 10-11
general release specification august 28, 1998 motorola mc68hc705jb2 viii rev 1.1 list of figures figure title page 10-12 low speed driver signal waveforms .......................................................... 10-12 10-13 differential input sensitivity over entire common mode range ................. 10-13 10-14 data jitter..................................................................................................... 10-14 10-15 data signal rise and fall time.................................................................... 10-14 10-16 nrzi data encoding .................................................................................... 10-16 10-17 flow diagram for nrzi ................................................................................ 10-16 10-18 bit stuffing.................................................................................................... 10-16 10-19 flow diagram for bit stuffing ....................................................................... 10-17 10-20 usb address register (uaddr) ................................................................. 10-19 10-21 usb interrupt register 0 (uir0) .................................................................. 10-19 10-22 usb interrupt register 1(uir1) ................................................................... 10-20 10-23 usb control register 0 (ucr0)................................................................... 10-22 10-24 usb control register 1 (ucr1)................................................................... 10-23 10-25 usb control register 2 (ucr2)................................................................... 10-24 10-26 usb status register (usr) ......................................................................... 10-25 10-27 usb endpoint 0 data register (ue0d0-ue0d7)......................................... 10-26 10-28 usb endpoint 1/endpoint2 data registers (ue1d0-ue1d7)...................... 10-26 10-29 out token data flow for receive endpoint 0 ............................................ 10-29 10-30 setup token data flow for receive endpoint 0........................................ 10-30 10-31 in token data flow for transmit endpoint 0 ............................................... 10-31 10-32 in token data flow for transmit endpoint 1/ endpoint 2............................ 10-32 11-1 eprom programming sequence .................................................................. 11-3 14-1 20-pin pdip mechanical dimensions ............................................................ 14-1 14-2 20-pin soic mechanical dimensions ............................................................ 14-2
list of tables table title page august 28, 1998 general release specification mc68hc705jb2 motorola rev 1.1 ix 4-1 reset/interrupt vector addresses .................................................................... 4-2 7-1 port a i/o pin functions................................................................................... 7-7 7-2 port b i/o pin functions................................................................................... 7-7 10-1 supported packet identifiers .......................................................................... 10-5 10-2 register summary ....................................................................................... 10-18 11-1 operation mode condition after reset .......................................................... 11-1 12-1 register/memory instructions ........................................................................ 12-4 12-2 read-modify-write instructions...................................................................... 12-5 12-3 jump and branch instructions........................................................................ 12-6 12-4 bit manipulation instructions .......................................................................... 12-7 12-5 control instructions ........................................................................................ 12-7 12-6 instruction set summary............................................................................... 12-8 12-7 opcode map................................................................................................. 12-14 13-1 maximum ratings .......................................................................................... 13-1 13-2 thermal characteristics ................................................................................. 13-1 13-3 dc electrical characteristics.......................................................................... 13-2 13-4 usb dc electrical characteristics ................................................................. 13-3 13-5 usb low speed source electrical characteristics ........................................ 13-4 13-6 control timing................................................................................................ 13-5 13-7 eprom programming electrical characteristics ........................................... 13-5
general release specification august 28, 1998 motorola mc68hc705jb2 x rev 1.1 list of tables table title page
august 28, 1998 general release specification mc68hc705jb2 general description motorola rev 1.1 1-1 section 1 general description the mc68hc705jb2 is a member of the low-cost, high-performance mc68hc05 family of 8-bit microcontroller units (mcus). the mc68hc05 family is based on the customer-speci?d integrated circuit (csic) design strategy. all mcus in the family use the popular mc68hc05 central processing unit (cpu) and are available with a variety of subsystems, memory sizes and types, and package types. the mc68hc705jb2 is speci?ally designed to be used in applications where a universal serial bus (usb) interface is required. 1.1 features industry standard m68hc05 cpu core memory-mapped input/output (i/o) registers 2048 bytes of user eprom 128 bytes of user ram fully compliant low speed usb with 3 endpoints: 1 control endpoint (2 x 8-byte buffer) 2 interrupt endpoints (1 x 8-byte buffer shared) 3.3volt dc output pin for usb pullup resistors multi-function timer 16-bit input capture/output compare timer 11 bidirectional i/o pins with the following features: 9 i/os have software programmable pull-down capability 2 open-drain i/os have software programmable pull-up, 25ma current sink capability 4 i/os with external interrupt capability low voltage reset (lvr) circuit power saving stop and wait modes available in 20-pin pdip and 20-pin soic packages
general release specification august 28, 1998 motorola general description mc68hc705jb2 1-2 rev 1.1 1.2 mask options the mask options on the mc68hc705jb2 are handled with ?e eprom bits in the mask option register ($01ff). these options are: external interrupt pins (irq , pa0 to pa3): [edge-triggered or edge-and-level-triggered] port a and port b pull-down/pull-up resistors: [connected or disconnected] pa0-pa3 external interrupt capability: [enabled or disabled] osc, crystal/ceramic resonator startup delay: [4064 or 128 internal bus cycles] low voltage reset (lvr): [enabled or disabled] to program the mor, the moron bit in the program control register (bit 3 of $3e) must be set to ?? irqtrig ?irq, pa0-pa3 interrupt options 1 = edge-trigger only 0 = edge-and-level-triggered pullren ?port a and b pullup/pulldown options 1 = connected 0 = disconnected painten ?pa0-pa3 external interrupt options 1 = disabled 0 = enabled oscdly ?oscillator delay option 1 = 128 internal clock cycles 0 = 4064 internal clock cycles lvren ?lvr option 1 = enabled 0 = disabled bit-7 bit-6 bit-5 bit4 bit-3 bit-2 bit1 bit-0 mor $01ff read irqtrig pullren painten oscdly lvren write erased 0001 1 111 reset unaffected
august 28, 1998 general release specification mc68hc705jb2 general description motorola rev 1.1 1-3 1.3 mcu structure figure 1-1 shows the block diagram of the mc68hc705jb2. figure 1-1. mc68hc705jb2 block diagram 128 bytes ram 2048 bytes eprom low speed usb 16-bit timer core timer osc ? 2 reset and irq lvr vref power supply port a data direction reg. a port b data direction reg. b cpu control alu 68hc05 cpu accum index reg. cpu registers program counter cond code reg. 0 0 0 0 000 11 stk pntr 0 111hi nzc pa0 ? pa1 ? pa2 ? pa3 ? pa4 - pa5 - pa6 - pa7 - pb0 ? pb1 a pb2 a vdd vss 3.3v reset irq tcap ? d+ d osc1 osc2 - : 8 ma current sink capability a : 25 ma current sink, open-drained ? : external edge interrupt capability, with internal pullup, slow transition o/p ? : tcap is shared with pb0 with schmitt trigger input
general release specification august 28, 1998 motorola general description mc68hc705jb2 1-4 rev 1.1 figure 1-2. pin assignments for 20-pin package 1.4 functional pin descriptions the following paragraphs give a description of the general function of each pin assigned in figure 1-2 . 1.4.1 v dd , v ss power is supplied to the mcu through v dd and v ss . v dd is the positive supply, and v ss is ground. the mcu operates from a single power supply. very fast signal transitions occur on the mcu pins. the short rise and fall times place very high short-duration current demands on the power supply. to prevent noise problems, special care should be taken to provide good power supply bypassing at the mcu by using bypass capacitors with good high-frequency characteristics that are positioned as close to the mcu as possible. bypassing requirements vary, depending on how heavily the mcu pins are loaded. 1.4.2 osc1, osc2 the osc1 and osc2 pins are the connections for the on-chip oscillator. the osc1 and osc2 pins can accept the following sets of components: reset 1 pa0 2 pa1 3 pa2 4 pa3 5 pa4 6 pb0/tcap 7 pb1 8 vdd 20 osc1 19 osc2 18 vss 17 3.3v 16 d+ 15 d 14 pa7 13 pa6 12 pa5 11 irq /vpp 10 pb2 9
august 28, 1998 general release specification mc68hc705jb2 general description motorola rev 1.1 1-5 1. a crystal as shown in figure 1-3 (a) 2. a ceramic resonator as shown in figure 1-3 (a) 3. an external clock signal as shown in figure 1-3 (b) the frequency, f osc , of the oscillator or external clock source is divided by two to produce the internal operating frequency, f op . if the internal operating frequency is 3mhz, then the external oscillator frequency will be 6mhz. for ls usb 1.5mhz frequency clock can be derived from a divided by 4 circuit. the type of oscillator is selected by a mask option. 1.4.2.1 crystal oscillator the circuit in figure 1-3 (a) shows a typical oscillator circuit for an at-cut, parallel resonant crystal. the crystal manufacturers recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. the load capacitance values used in the oscillator circuit design should include all stray capacitances. the crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. an internal start-up resistor of typically 2m w is provided between osc1 and osc2 for the crystal type oscillator. figure 1-3. oscillator connections 1.4.2.2 ceramic resonator oscillator in cost-sensitive applications, a ceramic resonator can be used in place of the crystal. the circuit in figure 1-3 (a) can be used for a ceramic resonator. the resonator manufacturers recommendations should be followed, as the resonator parameters determine the external component values required for maximum stability and reliable starting. the load capacitance values used in the oscillator circuit design should include all stray capacitances. the ceramic resonator and mcu 37 pf 37 pf 2m w unconnected external clock osc1 osc2 mcu (a) crystal or ceramic resonator connections (b) external clock source connection osc1 osc2
general release specification august 28, 1998 motorola general description mc68hc705jb2 1-6 rev 1.1 components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. an internal start-up resistor of 2m w (typical) is provided between osc1 and osc2 for the ceramic resonator type oscillator. 1.4.2.3 external clock an external clock from another cmos-compatible device can be connected to the osc1 input, with the osc2 input not connected, as shown in figure 1-3 (b). 1.4.3 re set this is an i/o pin. this pin can be used as an input to reset the mcu to a known start-up state by pulling it to the low state. the reset pin contains a steering diode to discharge any voltage on the pin to v dd , when the power is removed. an internal pull-up is also connected between this pin and v dd . the reset pin contains an internal schmitt trigger to improve its noise immunity as an input. this pin is an output pin if lvr triggers an internal reset. 1.4.4 irq /vpp this input pin drives the asynchronous irq interrupt function of the cpu. the irq interrupt function has a mask option to provide either only negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. if the option is selected to include level-sensitive triggering, the irq input requires an external resistor to v dd for "wired-or" operation, if desired. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. note each of the pa0 thru pa3 i/o pins may be connected as an or function with the irq interrupt function by a mask option. this capability allows keyboard scan applications where the transitions or levels on the i/o pins will behave the same as the irq pin, except for the inverted phase. the edge or level sensitivity selected by a separate mask option for the irq pin also applies to the i/o pins or?d to create the irq signal. in bootloader mode, this pin (vpp) is used to supply the required programming voltage to the eprom array.
august 28, 1998 general release specification mc68hc705jb2 general description motorola rev 1.1 1-7 1.4.5 pa0-pa7 these eight i/o lines comprise porta. pa0 to pa7 are push-pull pins with pulldown devices. pa4 to pa7 are also capable of sinking 8 ma. the state of any pin is software programmable and all port a lines are con?ured as inputs during power-on or reset. the lower four i/o pins (pa0 thru pa3) can be connected via an internal or gate to the irq interrupt function enabled by a mask option. see section 7 on input/output ports for further details. 1.4.6 pb0-pb2 these three i/o lines comprise port b. pb1 and pb2 are open-drain i/o lines with pullup devices, whereas pb0 (shared with tcap), is a push-pull i/o line with pulldown device. the state of any pin is software programmable and is con?ured as an input during power-on or reset. pb1 and pb2 are also slow transition outputs, each capable of sinking 25ma typical current at 0.5v v ol max. see section 7 on input/output ports for further details. 1.4.7 d+, d d+ and d?are the differential data lines used by the usb module. see section 10 on universal serial bus module. 1.4.8 3.3v this is the 3.3v output of the on-chip voltage regulator from the mcu. it is used to supply the voltage for the external pullup resistor required by the usb on d? this regulator output is also used internally for the usb data driver circuitry. this 3.3v pin should be decoupled using a 1 m f (or greater) capacitor and a 0.1 m f bypass capacitor.
general release specification august 28, 1998 motorola general description mc68hc705jb2 1-8 rev 1.1
august 28, 1998 general release specification mc68hc705jb2 memory motorola rev 1.1 2-1 section 2 memory 2.1 memory map the mc68hc705jb2 has an 8-kbyte memory map consisting of user eprom, ram, burn-in rom, and input/output (i/o), as shown in figure 2-1 . figure 2-1. mc68hc705jb2 memory map unimplemented 64 bytes 5632 1535 8191 7679 user ram 128 bytes reset vector (low byte) reset vector (high byte) swi vector (low byte) swi vector (high byte) irq vector (low byte) irq vector (high byte) usb vector (low byte) usb vector (high byte) $1ff7 $1ff8 $1ff9 $1ffa $1ffb $1ffc $1ffd $1ffe $1fff $003f $0000 $00ff 0255 i/o 64 bytes 0064 0063 0000 $1fff $1fef $1600 $05ff $0080 $007f $0040 $003f $0000 user eprom 2048 bytes i/o registers total 64 bytes (see figure 2-2 ) 0128 0127 unimplemented 5276 bytes $1ff6 $1ff3 $1ff4 $1ff5 $1ff2 $1ff1 $1ff0 reserved $1dff $1e00 7680 8175 bootstrap rom 496 bytes timer1 vector (low byte) mft vector (low byte) timer1 vector (high byte) mft vector (high byte) reserved reserved reserved mor register $01ff eprom program control reserved $003e $00c0 stack unimplemented user vectors 16 bytes
general release specification august 28, 1998 motorola memory mc68hc705jb2 2-2 rev 1.1 2.2 i/o and control registers the i/o and control registers reside at locations $0000-$003f. the outline of these registers are shown in figure 2-2 . the bit assignments for each register are shown in figure 2-3 , figure 2-4 , and figure 2-5 . reading from unimplemented bits will return unknown states, and writing to unimplemented bits will be ignored. figure 2-2. i/o registers port a data register $0000 port b data register $0001 port a data direction register $0004 port b data direction register $0005 timer control & status register $0008 timer counter register $0009 reserved $01ff unimplemented (2) unimplemented (2) unimplemented (5) unimplemented (4) irq control & status register $000a port a pulldown register $0010 port b pulldown/up register $0011 $0020 to $0027 usb endpoint0 data registers (8) $0028 to $002f usb endpoint1 data registers (8) usb control2 register $0038 usb address register usb interrupt0 register $0039 $003a usb interrupt1 register $003b usb control0 register $003c usb control1 register $003d usb status register eprom program control register $0012 to timer1 registers (10) $003e $001b $0037 mask option register $003f
august 28, 1998 general release specification mc68hc705jb2 memory motorola rev 1.1 2-3 2.3 ram the user ram consists of 128 bytes (including the stack) located from $0080 to $00ff. the stack begins at address $00ff and proceeds down to $00c0. using the stack area for data storage or temporary work locations requires care to pre- vent it from being overwritten due to stacking from an interrupt or subroutine call. 2.4 eprom the on-chip user eprom consists of 2048 bytes of eprom from $1600 to $1dff and 16 bytes of user vectors from $1ff0 to $1fff. the bootloader rom and vectors are located from $1e00 to $1fef. 12 of the user vectors, $1ff4-$1fff, are dedicated to reset and interrupt vectors. the four remaining locations, $1ff0-$1ff3, are reserved for test functions. the mask option register is located at $01ff. 2.5 bootloader rom addresses $1e00 to $1fef are reserved rom addresses that contain the instructions for the bootloader functions. (see section 11 .)
general release specification august 28, 1998 motorola memory mc68hc705jb2 2-4 rev 1.1 addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0000 port a data r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 (porta) w $0001 port b data r pb2 pb1 pb0 (portb) w $0002 unimplemented r w $0003 unimplemented r w $0004 port a data dir r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 (ddra) w $0005 port b data dir r slowe ddrb2 ddrb1 ddrb0 (ddrb) w $0006 unimplemented r w $0007 unimplemented r w $0008 mft control & status (tcsr) r tof rtif tofe rtie 00 rt1 rt0 w tofr rtifr $0009 mft counter r tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 tcnt w $000a irq control & status (icsr) r irqe 0 0 0 irqf 0 0 0 w irqr $000b unimplemented r w $000c unimplemented r w $000d unimplemented r w $000e unimplemented r w $000f unimplemented r w figure 2-3. i/o registers $0000-$000f
august 28, 1998 general release specification mc68hc705jb2 memory motorola rev 1.1 2-5 addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0010 port a pulldown/up r (pdura) w pdra7 pdra6 pdra5 pdra4 pdra3 pdra2 pdra1 pdra0 $0011 port b pulldown/up r (pdurb) w purb2 purb1 purb0 $0012 timer control r icie ocie toie 0 0 0 iedg 0 (tcr) w $0013 timer status r icf ocf tof 00000 (tsr) w $0014 input capture high r bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 (ich) w $0015 input capture low r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (icl) w $0016 output compare high r bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 (och) w $0017 output compare low r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (ocl) w $0018 timer high r bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 (tcnth) w $0019 timer low r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (tcntl) w $001a alt counter high r bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 (acnth) w $001b alt counter low r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (acntl) w $001c unimplemented r w $001d unimplemented r w $001e unimplemented r w $001f unimplemented r w figure 2-4. i/o registers $0010-$001f
general release specification august 28, 1998 motorola memory mc68hc705jb2 2-6 rev 1.1 addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0020 to $0027 usb endpoint0 data reg. 0 to 7 r ue0rd7 ue0rd6 ue0rd5 ue0rd4 ue0rd3 ue0rd2 ue0rd1 ue0rd0 (ud0r0-7) w ue0td7 ue0td6 ue0td5 ue0td4 ue0td3 ue0td2 ue0td1 ue0td0 $0028 to $002f usb endpoint1 data reg. 0 to 7 r (ud1r0-7) w ue1td7 ue1td6 ue1td5 ue1td4 ue1td3 ue1td2 ue1td1 ue1td0 $0030 to $0036 unimplemented r w $0037 usb control2 r 0 tx1st 0 enable2 enable1 stall2 stall1 (ucr2) w tx1str $0038 usb address r usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 (uadr) w $0039 usb interrupt0 r txd0f rxd0f rstf suspnd txd0ie rxd0ie 00 (uir0) w 0 0 0 txd0fr rxd0fr $003a usb interrupt1 r txd1f eopf resumf 0 txd1ie eopie 00 (uir1) w 0 0 0 resumfr txd1fr eopfr $003b usb control 0 r t0seq stall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 (ucr0) w $003c usb control1 r t1seq endadd tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 (ucr1) w $003d usb status r rseq setup rpsiz3 rpsiz2 rpsiz1 rpsiz0 (usr) w $003e prog. control r moron elat pgm (pcr) w $003f reserved r w figure 2-5. i/o registers $0020-$003f addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $01ff mask option r irqtrig pullren painten oscdly lvren (mor) w figure 2-6. mask option register $01ff
august 28, 1998 general release specification mc68hc705jb2 central processing unit motorola rev 1.1 3-1 section 3 central processing unit the mc68hc705jb2 has a 8kbyte memory map. the stack has only 64 bytes. therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00c0 and then wrap-around to $00ff. all other instructions and registers behave as described in this chapter. 3.1 registers the mcu contains ?e registers which are hard-wired within the cpu and are not part of the memory map. these ?e registers are shown in figure 3-1 and are described in the following paragraphs. figure 3-1. mc68hc05 programming model condition code register i accumulator 60 a index register 71 x 4 52 3 stack pointer sp 14 8 15 9 12 13 10 11 pc cc 111 11 0 0 0 0 0 0 0 0 program counter h nzc half-carry bit (from bit 3) interrupt mask negative bit zero bit carry bit
general release specification august 28, 1998 motorola central processing unit mc68hc705jb2 3-2 rev 1.1 3.2 accumulator (a) the accumulator is a general purpose 8-bit register as shown in figure 3-1 . the cpu uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. the accumulator is not affected by a reset of the device. 3.3 index register (x) the index register shown in figure 3-1 is an 8-bit register that can perform two functions: indexed addressing temporary storage in indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. in indexed addressing with an 8-bit offset, the cpu ?ds the operand address by adding the index register content to an 8-bit immediate value. in indexed addressing with a 16-bit offset, the cpu ?ds the operand address by adding the index register content to a 16-bit immediate value. the index register can also serve as an auxiliary accumulator for temporary storage. the index register is not affected by a reset of the device. 3.4 stack pointer (sp) the stack pointer shown in figure 3-1 is a 16-bit register. in mcu devices with memory space less than 64 kbytes the unimplemented upper address lines are ignored. the stack pointer contains the address of the next free location on the stack. during a reset or the reset stack pointer (rsp) instruction, the stack pointer is set to $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled off the stack. when accessing memory, the ten most signi?ant bits are permanently set to 0000000011. the six least signi?ant register bits are appended to these ten ?ed bits to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64($c0) locations. if 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. a subroutine call occupies two locations on the stack and an interrupt uses ?e locations.
august 28, 1998 general release specification mc68hc705jb2 central processing unit motorola rev 1.1 3-3 3.5 program counter (pc) the program counter shown in figure 3-1 is a 16-bit register. in mcu devices with memory space less than 64 kbytes the unimplemented upper address lines are ignored. the program counter contains the address of the next instruction or operand to be fetched. normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.6 condition code register (ccr) the ccr shown in figure 3-1 is a 5-bit register in which four bits are used to indicate the results of the instruction just executed. the ?th bit is the interrupt mask. these bits can be individually tested by a program, and speci? actions can be taken as a result of their states. the condition code register should be thought of as having three additional upper bits that are always ones. only the interrupt mask is affected by a reset of the device. the following paragraphs explain the functions of the lower ?e bits of the condition code register. 3.6.1 half carry bit (h-bit) when the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last add or adc (add with carry) operation. the half-carry bit is required for binary-coded decimal (bcd) arithmetic operations. 3.6.2 interrupt mask (i-bit) when the interrupt mask is set, the internal and external interrupts are disabled. interrupts are enabled when the interrupt mask is cleared. when an interrupt occurs, the interrupt mask is automatically set after the cpu registers are saved on the stack, but before the interrupt vector is fetched. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. normally, the interrupt is processed as soon as the interrupt mask is cleared. a return from interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. after any reset, the interrupt mask is set and can only be cleared by the clear i-bit (cli), or wait instructions. 3.6.3 negative bit (n-bit)
general release specification august 28, 1998 motorola central processing unit mc68hc705jb2 3-4 rev 1.1 the negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (bit 7 of the result was a logical one.) the negative bit can also be used to check an often tested ?g by assigning the ?g to bit 7 of a register or memory location. loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the ?g. 3.6.4 zero bit (z-bit) the zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero. 3.6.5 carry/borrow bit (c-bit) the carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. the carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. this bit is neither set by an inc nor by a dec instruction.
august 28, 1998 general release specification mc68hc705jb2 interrupts motorola rev 1.1 4-1 section 4 interrupts the mcu can be interrupted in six different ways: non-maskable software interrupt instruction (swi) external interrupt (irq ) optional external interrupt via irq on pa0-pa3 (mask option) usb interrupt timer1 interrupt (16-bit timer) multi-function timer interrupt 4.1 cpu interrupt processing interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. if interrupts are not masked (i-bit in the ccr is clear) and the corresponding interrupt enable bit is set the processor will proceed with interrupt processing. otherwise, the next instruction is fetched and executed. if an interrupt occurs the processor completes the current instruction, then stacks the current cpu register states, sets the i-bit to inhibit further interrupts, and ?ally checks the pending hardware interrupts. if more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in table 4-1 will be serviced ?st. the swi is executed the same as any other instruction, regardless of the i-bit state. when an interrupt is to be processed the cpu fetches the address of the appropriate interrupt software service routine from the vector table at locations $1ff4 to $1fff as de?ed in table 4-1 .
general release specification august 28, 1998 motorola interrupts mc68hc705jb2 4-2 rev 1.1 an rti instruction is used to signify when the interrupt software service routine is completed. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. figure 4-1 shows the sequence of events that occur during interrupt processing. 4.2 reset interrupt sequence the reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in figure 4-1 . a low level input on the reset pin or an internally generated rst signal causes the program to vector to its starting address which is speci?d by the contents of memory locations $1ffe and $1fff. the i-bit in the condition code register is also set. table 4-1. reset/interrupt vector addresses function source control bit global hardware mask local software mask priority (1 = highest) vector address reset power-on logic reset pin low voltage reset illegal address reset usb reset 1 $1ffe?1fff software interrupt (swi) user code same priority as instruction $1ffc?1ffd external interrupt (irq) irq pin i bit irqe bit 2 $1ffa?1ffb usb interrupts txd0f txd1f resumf i bit txd0ie txd1ie 3 $1ff8?1ff9 timer1 interrupts icf bit ocf bit tof bit i bit icie bit ocie bit toie bit 4 $1ff6?1ff7 mft interrupts tof bit rtif i bit tofe bit rtie bit 5 $1ff4?1ff5 reserved $1ff2?1ff3 reserved $1ff0?1ff1
august 28, 1998 general release specification mc68hc705jb2 interrupts motorola rev 1.1 4-3 figure 4-1. interrupt processing flowchart no external interrupt? i bit set? from reset yes yes clear irq latch. no execute instruction. unstack ccr, a, x, pch, pcl. fetch next instruction. stack pcl, pch, x, a, ccr. set i bit. load pc with interrupt vector. usb interrupt? yes no timer1 interrupt? yes no mft interrupt? yes no swi instruction? yes no rti instruction? yes no
general release specification august 28, 1998 motorola interrupts mc68hc705jb2 4-4 rev 1.1 4.3 software interrupt (swi) the swi is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the i-bit in the ccr. as with any instruction, interrupts pending during the previous instruction will be serviced before the swi opcode is fetched. the interrupt service routine address is speci?d by the contents of memory locations $1ffc and $1ffd. 4.4 hardware interrupts all hardware interrupts except reset are maskable by the i-bit in the ccr. if the i-bit is set, all hardware interrupts (internal and external) are disabled. clearing the i-bit enables the hardware interrupts. there are two types of hardware interrupts which are explained in the following sections. 4.4.1 external interrupt (irq ) the irq pin provides an asynchronous interrupt to the cpu. a block diagram of the irq function is shown in figure 4-2 . figure 4-2. external interrupt (irq) logic irq irq latch v dd rst irq vector fetch irq status/control register external interrupt request irqe irqf irqr internal data bus to bih & bil instruction processing r irq level (mask option) pa 0 pa 1 pa 2 pa 3 port a external interrupt (mask option)
august 28, 1998 general release specification mc68hc705jb2 interrupts motorola rev 1.1 4-5 the irq pin is one source of an irq interrupt and a mask option can also enable the four lower port a pins (pa0 thru pa3) to act as other irq interrupt sources. refer to figure 4-2 for the following descriptions. irq interrupt source comes from irq latch. the irq latch will be set on the falling edge of the irq pin or on any rising edge of pa0-3 pins if pa0-3 interrupts have been enabled. if "edge-only" sensitivity is chosen by a mask option, only the irq latch output can activate an irqf ?g which creates a request to the cpu to generate the irq interrupt sequence. this makes the irq interrupt sensitive to the following cases: falling edge on the irq pin. rising edge on any pa0-pa3 pin with irq enabled (via mask option). if level sensitivity is chosen, the active high state the signal to the clock input of the irq latch can also activate an irqf ?g which creates an irq request to the cpu to generate the irq interrupt sequence. this makes the irq interrupt sensitive to the following cases: low level on the irq pin. falling edge on the irq pin. high level on any pa0- pa3 pin with irq enabled (via mask option). rising edge on any pa0- pa3 pin with irq enabled (via mask option). the irqe enable bit controls whether an active irqf ?g can generate an irq interrupt sequence. this interrupt is serviced by the interrupt service routine located at the address speci?d by the contents of $1ffa and $1ffb. the irq latch is automatically cleared by entering the interrupt service routine if irqe enable bit is cleared. if irqe enable bit is also set, the only way of clearing irqf is by writing a logic one to the irqr acknowledge bit. writing a logic one to the irqr acknowledge bit in the icsr is the other way of clearing irqf ?g. as long as the output state of the irqf ?g bit is active the cpu will continuously re- enter the irq interrupt sequence until the active state is removed or the irqe enable bit is cleared. 4.4.2 irq control/status register (icsr) $0a the irq interrupt function is controlled by the icsr located at $000a. all unused bits in the icsr will read as logic zeros. the irqf bit is cleared and irqe bit is set by reset. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icsr r irqe 0 0 0 irqf 0 0 0 $000a w irqr reset: 10000000 figure 4-3. irq control and status register (icsr)
general release specification august 28, 1998 motorola interrupts mc68hc705jb2 4-6 rev 1.1 irqr - irq interrupt acknowledge the irqr acknowledge bit clears an irq interrupt by clearing the irq latch. the irqr acknowledge bit will always read as a logic zero. 1 = writing a logic one to the irqr acknowledge bit will clear the irq latch. 0 = writing a logic zero to the irqr acknowledge bit will have no effect on the irq latch. irqf - irq interrupt request flag writing to the irqf ?g bit will have no effect on it. if the additional setting of irqf ?g bit is not cleared in the irq service routine and the irqe enable bit remains set the cpu will re-enter the irq interrupt sequence continuously until either the irqf ?g bit or the irqe enable bit is clear. the irqf latch is cleared by reset. 1 = indicates that an irq request is pending. 0 = indicates that no irq request triggered by pins pa0-3 or irq is pending. the irqf ?g bit is cleared once the irq vector is fetched. the irqf ?g bit can be cleared by writing a logic one to the irqr acknowledge bit to clear the irq latch and also conditioning the external irq sources to be inactive (if the level sensitive interrupts are enabled via mask option). doing so before exiting the service routine will mask out additional occurrences of the irqf. irqe - irq interrupt enable the irqe bit enables/disables the irqf ?g bit to initiate an irq interrupt sequence. 1 = enables irqf interrupt, that is, the irqf ?g bit can generate an interrupt sequence. reset sets the irqe enable bit, thereby enabling irq interrupts once the i-bit is cleared. execution of the stop or wait instructions causes the irqe bit to be set in order to allow the external irq to exit these modes. 0 = the irqf ?g bit cannot generate an interrupt sequence. 4.4.3 optional external interrupts (pa0-pa3) the irq interrupt can also be triggered by the inputs on the pa0 thru pa3 port pins if enabled by a single mask option. if enabled, the lower four bits of port a can activate the irq interrupt function, and the interrupt operation will be the same as for inputs to the irq pin. this mask option of pa0-3 interrupt allow all of these input pins to be or?d with the input present on the irq pin. all pa0 thru pa3 pins must be selected as a group as an additional irq interrupt. all the pa0-3 interrupt sources are also controlled by the irqe enable bit.
august 28, 1998 general release specification mc68hc705jb2 interrupts motorola rev 1.1 4-7 note the bih and bil instructions will only apply to the level on the irq pin itself, and not to the output of the logic or function with the pa0 thru pa3 pins. the state of the individual port a pins can be checked by reading the appropriate port a pins as inputs. note if enabled, the pa0 to pa3 pins will cause an irq interrupt regardless of whether these pins are con?ured as inputs or outputs. 4.4.4 timer1 interrupt (timer1) the timer interrupt is generated by the timer when either a timer1 over?w or a input capture or output compare has occurred as described in section 9 . the interrupt ?gs and enable bits for the timer1 interrupts are located in the timer1 control & status register (tsr) located at $0012, $0013. the i-bit in the ccr must be clear in order for the timer1 interrupt to be enabled. either of these three interrupts will vector to the same interrupt service routine located at the address speci?d by the contents of memory locations $1ff6 and $1ff7. 4.4.5 usb interrupt (usb) the usb interrupt is generated by the usb module as described in section 10 . the interrupt enable bits for the usb interrupt are located at bit3-bit2 of uir0 reg and bit3-bit2 of uir1 reg. also once the device goes into suspend mode, any bus activities will cause the usb to generate an interrupt to cpu to come out from the suspend mode. the i-bit in the ccr must be clear in order for the usb interrupt to be enabled. either of these two interrupts will vector to the same interrupt service routine located at the address speci?d by the contents of memory locations $1ff8 and $1ff9. 4.4.6 mft interrupt (mft) the mft interrupt is generated by the mft module as described in section 8 . these interrupts will vector to the same interrupt service routine located at the address speci?d by the contents of memory locations $1ff4 and $1ff5.
general release specification august 28, 1998 motorola interrupts mc68hc705jb2 4-8 rev 1.1
august 28, 1998 general release specification mc68hc705jb2 resets motorola rev 1.1 5-1 section 5 resets the mcu can be reset in ?e ways: by an active low input to the reset pin, by initial power-on reset, by an usb reset, by an illegal address access, and by a low voltage reset function. the reset pin is an i/o pin as shown in figure 5-1 . the internal steering diode for discharge and pull-up device are not shown here. all the peripheral modules which drive external pins will be reset by the synchronous reset signal (rst) coming from a latch, which is synchronized to the internal bus clock and set by any of the ?e reset sources. figure 5-1. reset block diagram reset reset latch r power-on reset illegal address reset internal d internal clock s rst to cpu and low voltage reset v dd subsystems address bus usb reset detection
general release specification august 28, 1998 motorola resets mc68hc705jb2 5-2 rev 1.1 5.1 external reset (reset ) the reset pin is the only external source of a reset. this pin is connected to a schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. this external reset occurs whenever the reset pin is pulled below the lower threshold and remains in reset until the reset pin rises above the upper threshold. this active low input will generate the rst signal and reset the cpu and peripherals. this pin is also an output pin whenever the lvr triggers an internal reset. termination of the external reset input or the usb reset or lvr are the only reset sources that can alter the operating mode of the mcu. note activation of the rst signal is generally referred to as reset of the device, unless otherwise speci?d. 5.2 internal resets the four internally generated resets are the initial power-on reset function, the usb reset ?g reset, the illegal address detector reset and the low voltage reset (lvr). termination of the external reset input or lvr or usb reset or iladr are the reset sources that can alter the operating mode of the mcu. the other internal resets will not have any effect on the mode of operation when their reset state ends. 5.2.1 power-on reset (por) the internal por is generated on power-up to allow the clock oscillator to stabilize. the por is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). there is an oscillator stabilization delay of 128 or 4064 internal processor bus clock cycles (ph2) for ceramic resonator or crystal after the oscillator becomes active. the por will generate the rst signal which will reset the cpu. if any other reset function is active at the end of this 128 or 4064 cycle delay, the rst signal will remain in the reset condition until the other reset condition(s) end. 5.2.2 usb reset the usb reset is generated by a detection on the usb bus reset signal. for mc68hc705jb2, seeing a single-end zero on its upstream port for 4 to 8 bit times will set rstf bit in uir0 register. the detections will also generate the rst signal to reset the cpu and other peripherals in the mcu.
august 28, 1998 general release specification mc68hc705jb2 resets motorola rev 1.1 5-3 5.2.3 illegal address reset (iladr) the internal iladr reset is generated when an instruction opcode fetch occurs from an address which is not implemented in the ram ($0080 - $00ff) nor rom ($1600-$1fff). the iladr will generate the rst signal which will reset the cpu and other peripherals. if any other reset function is active at the end of the iladr reset signal, the rst signal will remain in the reset condition until the other reset condition(s) end. notice that iladr also forces the reset pin low 5.2.4 low voltage reset (lvr) the internal lvr reset is generated when v dd falls below the speci?d lvr trigger value v lv r for at least one t cyc . in typical applications, the power supply decoupling circuit will eliminate negative-going voltage glitches of less than one t cyc . this reset will hold the mcu in the reset state until v dd rises above v lv r . whenever v dd is above v lvr and below 4.2v, the mcu is guaranteed to operate although not within speci?ation. the output from the lvr is connected directly to the internal reset circuitry and also forces the reset pin low. the internal reset will be removed once the power supply voltage rises above v lv r , at which time a normal power-on-reset sequence occurs. lvr function will still be active during stop or suspend mode.
general release specification august 28, 1998 motorola resets mc68hc705jb2 5-4 rev 1.1
august 28, 1998 general release specification mc68hc705jb2 low power modes motorola rev 1.1 6-1 section 6 low power modes the mc68hc705jb2 has two low-power operating modes: stop mode and wait mode. the stop and wait instructions provide two modes that reduce the power required for the mcu by stopping various internal clocks and/or the oscillator. the ?w of the stop, and wait modes are shown in figure 6-1 . 6.1 stop mode execution of the stop instruction in this mode places the mcu in its lowest power consumption mode. in the stop mode the internal oscillator is turned off, halting all internal processing. execution of the stop instruction automatically clears the i-bit in the condition code register and sets the irqe enable bit in the irq control/status register so that the irq external interrupt is enabled. all other registers, including the other bits in the tcsr, and memory remain unaltered. all input/output lines remain unchanged. the mcu can be brought out of the stop mode by an irq external interrupt or a usb coming out from suspend mode interrupt (bus activity detection) or an externally generated reset, usb reset or an lvr reset. when exiting the stop mode the internal oscillator will resume after a 128 or 4064 internal processor clock cycle oscillator stabilization delay. 6.2 wait mode the wait instruction places the mcu in a low-power mode, which consumes more power than the stop mode. in the wait mode the internal processor clock is halted, suspending all processor and internal bus activity. execution of the wait instruction automatically clears the i-bit in the condition code register and sets the irqe enable bit in the irq control/status register so that the irq external interrupt is enabled. all other registers, memory, and input/output lines remain in their previous states. the wait mode may be exited when an external irq or a usb or timer1 or mft interrupt, an lvr reset or an external reset occurs.
general release specification august 28, 1998 motorola low power modes mc68hc705jb2 6-2 rev 1.1 figure 6-1. stop/wait flowchart stop external reset? external interrupt? no no start stabilization delay yes yes end of stabilization delay? yes no wait restart internal processor clock 1. load pc with reset vector or 2. service interrupt. a. save cpu registers on stack. b. set i bit in ccr. c. load pc with interrupt vector. no external reset? yes no external interrupt? yes no usb interrupt? yes reset or no yes yes no stop external oscillator, stop internal timer clock, reset start-up delay stop internal processor clock, clear i-bit in ccr, set irqe in icsr usb interrupt no yes irq or reset? restart external oscillator, irq timer1 interrupt? internal mft interrupt? internal external oscillator active, internal timer clock active stop internal processor clock, clear i-bit in ccr, set irqe in icsr
august 28, 1998 general release specification mc68hc705jb2 low power modes motorola rev 1.1 6-3 6.3 data-retention mode the contents of ram and cpu registers are retained at supply voltages as low as 2.0vdc. this is called the data-retention mode where the data is held, but the device is not guaranteed to operate. the reset pin must be held low during data-retention mode. note the voltage threshold of the lvr is higher than the data-retention mode minimum voltage, therefore the data-retention mode will not be available if the lvr function is enabled in the mask option.
general release specification august 28, 1998 motorola low power modes mc68hc705jb2 6-4 rev 1.1
august 28, 1998 general release specification mc68hc705jb2 input/output ports motorola rev 1.1 7-1 section 7 input/output ports in the normal operating mode, there are 11 bidirectional i/o lines arranged as one 8-bit i/o port (port a), and one 3-bit i/o port (port b). each port line can be programed as either input or output, under software control, by the data direction registers (ddrs). also, if enabled by a mask option, all port a and port b i/o pins may have individual software programmable pulldown or pullup devices. pa4 to pa7 and pb1 & pb2 pins have the additional properties of sinking higher current. pa0 to pa3 may function as additional irq interrupt input sources (mask option). pb1 and pb2 have open drain output drivers, with optional slow falling-edge output transitions. the transition delay is 170ns (typical), with a bus rate of 3mhz and a loading of 50pf.
general release specification august 28, 1998 motorola input/output ports mc68hc705jb2 7-2 rev 1.1 7.1 port a port a is an 8-bit bidirectional port which shares four of its pins with the irq interrupt system as shown in figure 7-1 . each port a pin is controlled by the corresponding bits in a data direction register, a data register, and a pulldown register. the port a data register is located at address $0000. the port a data direction register (ddra) is located at address $0004. the port a pulldown register (pdura) is located at address $0010. reset clears the ddra and the pdura. the port a data register is unaffected by reset. figure 7-1. port a i/o circuitry 7.1.1 port a data register each port a i/o pin has a corresponding bit in the port a data register. when a port a pin is programmed as an output the state of the corresponding data register bit determines the state of the output pin. when a port a pin is programmed as an input, any read of the port a data register will return the logic state of the corresponding i/o pin. the port a data register is unaffected by reset. 7.1.2 port a data direction register each port a i/o pin may be programmed as an input by clearing the corresponding bit in the ddra, or programmed as an output by setting the corresponding bit in the ddra. the ddra can be accessed at address $0004. the ddra is cleared by reset. write $0010 100 m a pulldown read $0000 write $0000 read $0004 data register bit pa0-pa3 only: to irq interrupt system 8 ma sink capability (bits 4-7 only) output mask option (software pulldown inhibit) internal hc05 data bus reset (rst) write $0004 data direction register bit pulldown register bit note: each i/o port pin can have pulldown device i/o pin
august 28, 1998 general release specification mc68hc705jb2 input/output ports motorola rev 1.1 7-3 7.1.3 port a pulldown register all port a i/o pins may have software programmable pulldown devices enabled by a mask option. if the pulldown/up mask option is selected, the pulldown is activated whenever the corresponding bit in the pdura is clear. if the corresponding bit in the pdura bit is set or the mask option for pulldown is not chosen, the pulldown will be disabled. a pulldown on an i/o pin is activated only if the i/o pin is programmed as an input. the pdura is a write-only register. any reads of location $0010 will return unde?ed results. since reset clears both the ddra and the pdura, all pins will initialize as inputs with the pulldown active (if enabled by mask option). 7.1.4 port a drive capability the outputs of the pa4, pa5, pa6 and pa7 are capable of sinking 8 ma (typical) of current to v ss . 7.1.5 port a i/o pin interrupts the inputs to pa0, pa1, pa2, pa3 may be connected to the irq input of the cpu if enabled by a mask option. pa0 to pa4 also has a schmitt trigger circuit implemented as part of its input circuitry. when connected as an alternate source of an irq interrupt, pa0-3 input pins will behave the same as the irq pin itself, except that their active state is a logical one or a rising edge. the irq pin has an active state that is a logical zero or a falling edge. if the mask option for edge-and-level trigger sensitivity interrupts are chosen, the presence of a logic one or occurrence of a rising edge on any one of the lower four port a pins will cause an irq interrupt request. if the edge-only sensitivity is selected, the occurrence of a rising edge on any one of the lower four port a pins will cause an irq interrupt request. as long as any one of the lower four port a irq inputs remains at a logic one level, the other of the lower four port a irq inputs are effectively ignored. note the bih and bil instructions will only apply to the level on the irq pin itself, and not to the internal irq input to the cpu. therefore bih and bil cannot be used to test the state of the lower four port a input pins as a group.
general release specification august 28, 1998 motorola input/output ports mc68hc705jb2 7-4 rev 1.1 7.2 port b port b is a 3-bit bidirectional port which functions as shown in figure 7-2 . each port b pin is controlled by the corresponding bits in a data direction register, a data register, and a pulldown/up register. the port b data register is located at address $0001. the port b data direction register (ddrb) is located at address $0005. the port b pulldown/up register (pdurb) is located at address $0011. reset clears the ddrb and the pdurb. the port b data register is unaffected by reset. pb0 is a standard push-pull i/o pin with pulldown option; and is shared with tcap. pb1 and pb2 are of open-drain type, with pullup option, each capable of sinking 25ma (typical) current at v ol 0.5v max. these two pins may be connected together to constitute a single pin capable of sinking 50ma (typical). in this case, both pb1 and pb2 data bits will have to be written with the same value at the same write cycle. figure 7-2. port b i/o circuitry 7.2.1 port b data register all port b i/o pins have a corresponding bit in the port b data register. when a port b pin is programmed as an output the state of the corresponding data register bit determines the state of the output pin. when a port b pin is programmed as an input, any read of the port b data register will return the logic state of the corresponding i/o pin. the port b data register is unaffected by reset. unused bits will always read as logic zeros, and any write to these bits will be ignored. the port b data register is unaffected by reset. write $0011 read $0001 write $0001 read $0005 write $0005 internal hc05 data bus 100 m a pulldown data register bit output mask option (software pulldown/up inhibit) reset (rst) data direction register bit pulldown/up register bit vdd 100k pullup note: each i/o port pin can have either pullup or pulldown device, but not both. pb1 and pb2 output drivers are of open-drain type i/o pin
august 28, 1998 general release specification mc68hc705jb2 input/output ports motorola rev 1.1 7-5 7.2.2 port b data direction register port b i/o pins may be programmed as an input by clearing the corresponding bit in the ddrb, or programmed as an output by setting the corresponding bit in the ddrb. the ddrb can be accessed at address $0005. unused bits will always read as logic zeros, and any write to these bits will be ignored. the ddrb is cleared by reset. if con?ured as output pins, pb1 and pb2 have slow output falling-edge transition feature. the slow transition feature is controlled by the slowe bit of ddrb. slowe bit, if set and if the pin is con?ured as an output pin, enables the slow falling-edge output transition feature of pb1 and pb2. 7.2.3 slow output falling-edge transition slowe - slow transition enable the slow transition feature is controlled by the slowe bit of ddrb (port b data direction register). default value of slowe bit is clear on reset. 1 = enables the slow falling-edge output transition feature on both pb1 and pb2, if the pin is con?ured as an output pin. pb2 falling edge transition is a sharp falling edge transition delayed by t cyc /2 after the write cycle to pb2 data register. pb1 is a true slow transition i/o line. 0 = disables slow falling-edge output transition feature on both pb1 and pb2. 7.2.4 port b pulldown/pullup register all port b i/o pins may have software programmable pulldown/pullup devices enabled by a mask option. if the pulldown/pullup mask option is selected, the pulldown/pullup is activated whenever the corresponding bit in the pdurb is clear. a pulldown on an i/o pin is activated only if the i/o pin is programmed as an input; whereas a pullup device on an i/o pin is always activated whenever enabled, regardless of port direction. the pdurb is a write-only register. any reads of location $0011 will return unde?ed results. since reset clears both the ddrb and the pdurb, all pins will initialize as inputs with the pulldown devices active and pullup devices active (if chosen via mask option). typical value of pb1 and pb2 pullup is 100k w (typical). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ddrb r slowe ddrb2 ddrb1 ddrb0 $0005 w reset: 00000000 figure 7-3. port b data direction register
general release specification august 28, 1998 motorola input/output ports mc68hc705jb2 7-6 rev 1.1 7.3 i/o port programming all i/o pins can be programmed as inputs or outputs, with or without pulldown/ pullup devices. 7.3.1 pin data direction the direction of a pin is determined by the state of its corresponding bit in the associated port data direction register (ddr). a pin is con?ured as an output if its corresponding ddr bit is set to a logic one. a pin is con?ured as an input if its corresponding ddr bit is cleared to a logic zero. the data direction bits ddrb0 thru ddrb2 and ddra0 thru ddra7 are read/ write bits which can be manipulated with read-modify-write instructions. at power- on or reset, all ddrs are cleared which con?ures all port pins as inputs. if the pulldown/up mask option is chosen, all pins will initially power-up with their software programmable pulldown/ups enabled. 7.3.2 output pin when an i/o pin is programmed as an output pin, the state of the corresponding data register bit will determine the state of the pin. the state of the data register bits can be altered by writing to address $0000 for port a and address $0001 for port b. reads of the corresponding data register bit at address $0000 or $0001 will return the state of the data register bit (not the state of the i/o pin itself). therefore bit manipulation is possible on all pins programmed as outputs. if the corresponding bit in the pulldown/up register is clear (and the pulldown/up mask option is chosen), only output pins with pullups have an activated pullup device connected to the pin. for those pins with pulldowns and con?ured as output pins, the pulldowns will be inactivated regardless of the state of the corresponding pulldown/up register bit. since the pulldown/up register bits are write-only, bit manipulation should not be used on these register bits. 7.3.3 input pin when an i/o pin is programmed as an input pin, the state of the pin can be determined by reading the corresponding data register bit. any writes to the corresponding data register bit for an input pin will be ignored in the sense that the written value will not be re?cted on the pin, rather it is only re?cted in the port data register. please refer to table 7-1 and table 7-2 for details. if the corresponding bit in the pulldown/up register is clear (and the pulldown/up mask option is chosen) the input pin will also have an activated pulldown/up device. since the pulldown/up register bits are write-only, bit manipulation should not be used on these register bits.
august 28, 1998 general release specification mc68hc705jb2 input/output ports motorola rev 1.1 7-7 7.3.4 i/o pin transitions a "glitch" can be generated on an i/o pin when changing it from an input to an output unless the data register is ?st preconditioned to the desired state before changing the corresponding ddr bit from a zero to a one. if pulldowns are enabled by mask option, a ?ating input can be avoided by clearing the pulldown/pullup register bit before changing the corresponding ddr from a one to a zero. this will insure that the pulldown device will be activated before the i/o pin changes from a driven output to a pulled low/high input. 7.3.5 i/o pin truth tables every pin on port a and port b may be programmed as an input or an output under software control as shown in table 7-1 and table 7-2 . all port i/o pins may also have software programmable pulldown/pullup devices if selected by the appropriate mask option. table 7-1. port a i/o pin functions table 7-2. port b i/o pin functions accesses to pdura at $0010 accesses to data register @ $0000 0 1 in, hi-z out pdura0-7 pdura0-7 ddra0-7 ddra0-7 i/o pin pa0-7 * pa0-7 u u i/o pin mode ddra read/write accesses to ddra @ $0004 read write note: u is undefined. read write * does not affect input, but stored to data register accesses to pdurb at $0011 accesses to data register @ $0001 0 1 in, hi-z out pdurb0-2 pdurb0-2 ddrb0-2 ddrb0-2 i/o pin pb0-2 * pb0-2 u u i/o pin mode ddra read/write accesses to ddrb @ $0005 read write read write * does not affect input, but stored to data register note: u is undefined.
general release specification august 28, 1998 motorola input/output ports mc68hc705jb2 7-8 rev 1.1
august 28, 1998 general release specification mc68hc705jb2 multi-function timer motorola rev 1.1 8-1 section 8 multi-function timer the mc68hc705jb2 core timer is a multi-function ripple counter. the features include timer over flow (tof) and power-on reset (por). figure 8-1. multi-function timer block diagram as shown in figure 8-1 , the timer is driven by the timer clock, ntf1, divided by four ( ? 4). ntf1 has the same phase and frequency as the processor bus clock, ph2, but is not stopped by the wait modes. this signal drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time by accessing the timer counter register (tcnt) at address $09. a timer over?w rti select circuit overflow circuit detect 88 f op ? 2 2 ? 2 10 internal timer clock (ntf1) tof rtif tofe rtie rt1 rt0 rtifr tofr timer control & status register ($08) timer counter register ($09) interrupt circuit 7-bit counter mcu internal bus to cpu interrupt ? 2 14 ? 2 15 ? 2 17 ? 2 16 ? 4
general release specification august 28, 1998 motorola multi-function timer mc68hc705jb2 8-2 rev 1.1 function is implemented on the last stage of this counter, giving a possible interrupt at the rate of f op /1024. two additional stages produce the por function at f op /4064. the timer counter bypass circuitry (available only in expanded test mode) is at this point in the timer chain. this circuit is followed by two more stages, with the resulting clock (f op /16384) driving the real time interrupt circuit. the rti circuit consists of three divider stages with a 1 of 4 selector. the rti rate selector bits, and the rti and tof enable bits and ?gs are located in the timer control and status register at location $08. the real time interrupt circuit consists of a three stage divider and a 1 of 4 selector. the clock frequency that drives the rti circuit is f op /2 14 (or f op /16384) with three additional divider stages giving a maximum interrupt period of f op /2 17 (or f op /131072). the power-on cycle clears the entire counter chain and begins clocking the counter. after 128 or 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer will start counting up from zero and normal device operation will begin. if reset is asserted at any time during operation the counter chain will be cleared. 8.1 timer registers the 15-stage multi-function timer contains two registers: a timer counter register and a timer control/status register. 8.1.1 timer counter register (tcnt) $09 the timer counter register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked at f op divided by 4 and can be used for various functions including a software input capture. extended time periods can be attained using the tof function to increment a temporary ram storage location thereby simulating a 16- bit (or more) counter. the value of each bit of the tcnt is shown in figure 8-2 . this register is cleared by reset. figure 8-2. timer counter register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcnt r tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 $0009 w reset: 00000000
august 28, 1998 general release specification mc68hc705jb2 multi-function timer motorola rev 1.1 8-3 8.1.2 timer control/status register (tcsr) $08 the tcsr contains the timer interrupt ?g bits, the timer interrupt enable bits, and the real time interrupt rate select bits. bit 2 and bit 3 are write-only bits which will read as logical zeros. figure 8-3 shows the value of each bit in the tcsr following reset. figure 8-3. timer control/status register (tcsr) tof - timer over?w flag the tof is a read-only ?g bit. 1 = set when the 8-bit ripple counter rolls over from $ff to $00. a timer interrupt request will be generated if tofe is also set. 0 = reset by writing a logical one to the tof acknowledge bit, tofr. writing to the tof ?g bit has no effect on its value. this bit is cleared by reset. rtif - real time interrupt flag the rtif is a read-only ?g bit. 1 = set when the output of the chosen (1 of 4 selections) real time interrupt stage goes active. a timer interrupt request will be generated if rtie is also set. 0 = reset by writing a logical one to the rtif acknowledge bit, rtifr. writing to the rtif ?g bit has no effect on its value. this bit is cleared by reset. tofe - timer over?w enable the tofe is an enable bit that allows generation of a timer interrupt upon over?w of the timer counter register. 1 = when set, the timer interrupt is generated when the tof ?g bit is set. 0 = when cleared, no timer interrupt caused by tof bit set will be generated. this bit is cleared by reset. rtie - real time interrupt enable the rtie is an enable bit that allows generation of a timer interrupt by the rtif bit. 1 = when set, the timer interrupt is generated when the rtif ?g bit is set. 0 = when cleared, no timer interrupt caused by rtif bit set will be generated. this bit is cleared by reset. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcsr r tof rtif tofe rtie 00 rt1 rt0 $0008 w tofr rtifr reset: 00000011
general release specification august 28, 1998 motorola multi-function timer mc68hc705jb2 8-4 rev 1.1 tofr - timer over?w acknowledge the tofr is an acknowledge bit that resets the tof ?g bit. this bit is unaffected by reset. reading the tofr will always return a logical zero. 1 = clears the tof ?g bit. 0 = does not clear the tof ?g bit. rtifr - real time interrupt acknowledge the rtifr is an acknowledge bit that resets the rtif ?g bit. this bit is unaffected by reset. reading the rtifr will always return a logical zero. 1 = clears the rtif ?g bit. 0 = does not clear the rtif ?g bit. rt1, rt0 - real time interrupt period select bits these two bits select one of the four real time interrupt periods. 8.2 operation during stop mode when stop is exited by an external interrupt or an lvr reset or an external reset , the internal oscillator will resume, followed by a 128 or 4064 internal processor oscillator stabilization delay. bus frequency, f bus =f op =3.0 mhz rt1 rt0 divide ratio rti rate 00 2 14 5.46ms 01 2 15 10.92ms 10 2 16 21.85ms 11 2 17 43.69ms
august 28, 1998 general release specification mc68hc705jb2 programmable timer motorola rev 1.1 9-1 section 9 programmable timer this 16-bit programmable timer (timer1) has an input capture function and an output compare function. figure 9-1 shows a block diagram of the 16-bit programmable timer. figure 9-1. programmable timer block diagram iedg icie ocie toie tmrh ($0018) tmrl ($0019) 16-bit counter ? 4 internal (f osc ? 2) timer control register timer request overflow (tof) reset clock interrupt acrh ($001a) acrl ($001b) 16-bit comparator ocrh ($0016) ocrl ($0017) tcap edge select & detect icf ocf tof timer status register iedg icf ocf $0012 $0013 internal data bus logic icrh ($0014) icrl ($0015)
general release specification august 28, 1998 motorola programmable timer mc68hc705jb2 9-2 rev 1.1 the basis of the 16-bit timer is a 16-bit free-running counter which increases in count with each internal bus clock cycle. the counter is the timing reference for the input capture and output compare functions. the input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. software can read the value in the 16-bit free-running counter at any time without affect the counter sequence. because of the 16-bit timer architecture, the i/o registers for the input capture and output compare functions are pairs of 8-bit registers. each register pair contains the high and low byte of that function. generally, accessing the low byte of a speci? timer function allows full control of that function; however, an access of the high byte inhibits that speci? timer function until the low byte is also accessed. because the counter is 16 bits long and preceded by a ?ed divide-by-four prescaler, the counter rolls over every 262,144 internal clock cycles. timer resolution with a 4mhz crystal oscillator is 2 microsecond/count. the interrupt capability, the input capture edge, and the output compare state are controlled by the timer control register (tcr) located at $0012 and the status of the interrupt ?gs can be read from the timer status register (tsr) located at $0013. 9.1 timer registers (tmrh, tmrl) the functional block diagram of the 16-bit free-running timer counter and timer registers is shown in figure 9-2 . the timer registers include a transparent buffer latch on the lsb of the 16-bit timer counter. figure 9-2. programmable timer counter block diagram toie tmrh ($0018) tmr lsb 16-bit counter ? 4 internal (f osc ? 2) timer control reg. timer request overflow (tof) reset clock interrupt tmrl ($0019) tof timer status reg. $0012 $0013 internal ($fffc) data read tmrh read tmrl read latch bus
august 28, 1998 general release specification mc68hc705jb2 programmable timer motorola rev 1.1 9-3 the timer registers (tmrh, tmrl) shown in figure 9-3 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. writing to the timer registers has no effect. reset of the device presets the timer counter to $fffc. the tmrl latch is a transparent read of the lsb until the a read of the tmrh takes place. a read of the tmrh latches the lsb into the tmrl location until the tmrl is again read. the latched value remains ?ed even if multiple reads of the tmrh take place before the next read of the tmrl. therefore, when reading the msb of the timer at tmrh the lsb of the timer at tmrl must also be read to complete the read sequence. during power-on-reset (por), the counter is initialized to $fffc and begins counting after the oscillator start-up delay. because the counter is sixteen bits and preceded by a ?ed divide-by-four prescaler, the value in the counter repeats every 262, 144 internal bus clock cycles (524, 288 oscillator cycles). when the free-running counter rolls over from $ffff to $0000, the timer over?w ?g bit (tof) is set in the tsr. when the tof is set, it can generate an interrupt if the timer over?w interrupt enable bit (toie) is also set in the tcr. the tof ?g bit can only be reset by reading the tmrl after reading the tsr. other than clearing any possible tof ?gs, reading the tmrh and tmrl in any order or any number of times does not have any effect on the 16-bit free-running counter. note to prevent interrupts from occurring between readings of the tmrh and tmrl, set the i bit in the condition code register (ccr) before reading tmrh and clear the i bit after reading tmrl. 9.2 alternate counter registers (acrh, acrl) the functional block diagram of the 16-bit free-running timer counter and alternate bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmrh r tmrh7 tmrh6 tmrh5 tmrh4 tmrh3 tmrh2 tmrh1 tmrh0 $0018 w reset: 11111111 tmrl r tmrl7 tmrl6 tmrl5 tmrl4 tmrl3 tmrl2 tmrl1 tmrl0 $0019 w reset: 11111100 figure 9-3. programmable timer counter registers (tmrh, tmrl)
general release specification august 28, 1998 motorola programmable timer mc68hc705jb2 9-4 rev 1.1 counter registers is shown in figure 9-4 . the alternate counter registers behave the same as the timer registers, except that any reads of the alternate counter will not have any effect on the tof ?g bit and timer interrupts. the alternate counter registers include a transparent buffer latch on the lsb of the 16-bit timer counter. figure 9-4. alternate counter block diagram the alternate counter registers (acrh, acrl) shown in figure 9-5 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. writing to the alternate counter registers has no effect. reset of the device presets the timer counter to $fffc. the acrl latch is a transparent read of the lsb until the a read of the acrh takes place. a read of the acrh latches the lsb into the acrl location until the acrl is again read. the latched value remains ?ed even if multiple reads of the acrh take place before the next read of the acrl. therefore, when reading the msb of the timer at acrh the lsb of the timer at acrl must also be read to complete the read sequence. during power-on-reset (por), the counter is initialized to $fffc and begins counting after the oscillator start-up delay. because the counter is sixteen bits and preceded by a ?ed divide-by-four prescaler, the value in the counter repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles). reading the acrh and acrl in any order or any number of times does not have any effect on the 16-bit free-running counter or the tof ?g bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 acrh r acrh7 acrh6 acrh5 acrh4 acrh3 acrh2 acrh1 acrh0 $001a w reset: 11111111 acrl r acrl7 acrl6 acrl5 acrl4 acrl3 acrl2 acrl1 acrl0 $001b w reset: 11111100 figure 9-5. alternate counter registers (acrh, acrl) acrh ($001a) tmr lsb 16-bit counter ? 4 internal (f osc ? 2) reset clock acrl ($001b) internal ($fffc) data read acrh read acrl read latch bus
august 28, 1998 general release specification mc68hc705jb2 programmable timer motorola rev 1.1 9-5 note to prevent interrupts from occurring between readings of the acrh and acrl, set the i bit in the condition code register (ccr) before reading acrh and clear the i bit after reading acrl. 9.3 input capture registers the input capture function is a technique whereby an external signal (connected to pb0/tcap pin) is used to trigger the 16-bit timer counter. in this way it is possible to relate the timing of an external signal to the internal counter value, and hence to elapsed time. when the input capture circuitry detects an active edge on the tcap pin, it latches the contents of the free-running timer counter registers into the input capture registers as shown in figure 9-6 . latching values into the input capture registers at successive edges of the same polarity measures the period of the selected input signal. latching the counter values at successive edges of opposite polarity measures the pulse width of the signal. figure 9-6. timer input capture block diagram the input capture registers are made up of two 8-bit read-only registers (icrh, icrl) as shown in figure 9-7 . the input capture edge detector contains a schmitt icie icrh ($0014) 16-bit counter ? 4 internal (f osc ? 2) timer control reg. timer request input capture (icf) reset clock interrupt icrl ($0015) icf timer status reg. $0012 $0013 internal ($fffc) data read icrh read icrl latch bus iedg edge select & detect logic iedg pb0/tcap internal data bus
general release specification august 28, 1998 motorola programmable timer mc68hc705jb2 9-6 rev 1.1 trigger to improve noise immunity. the edge that triggers the counter transfer is de?ed by the input edge bit (iedg) in the tcr. reset does not affect the contents of the input capture registers. the result obtained by an input capture will be one count higher than the value of the free-running timer counter preceding the external transition. this delay is required for internal synchronization. resolution is affected by the prescaler, allowing the free-running timer counter to increment once every four internal clock cycles (eight oscillator clock cycles). reading the icrh inhibits further captures until the icrl is also read. reading the icrl after reading the timer status register (tsr) clears the icf ?g bit. does not inhibit transfer of the free-running counter. there is no con?ct between reading the icrl and transfers from the free-running timer counters. the input capture registers always contain the free-running timer counter value which corresponds to the most recent input capture. note to prevent interrupts from occurring between readings of the icrh and icrl, set the i bit in the condition code register (ccr) before reading icrh and clear the i bit after reading icrl. 9.4 output compare registers the output compare function is a means of generating an interrupt when the 16- bit timer counter reaches a selected value as shown in figure 9-8 . software writes the selected value into the output compare registers. on every fourth internal clock cycle (every eight oscillator clock cycle) the output compare circuitry compares the value of the free-running timer counter to the value written in the output compare registers. when a match occurs, the output compare interrupt ?g, ocf is set. a timer interrupt request to the cpu is generated if the output compare interrupt enable is set, i.e. ocie=1. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icrh r icrh7 icrh6 icrh5 icrh4 icrh3 icrh2 icrh1 icrh0 $0014 w reset: uuuuuuuu icrl r icrl7 icrl6 icrl5 icrl4 icrl3 icrl2 icrl1 icrl0 $0015 w reset: uuuuuuuu u = unaffected by reset figure 9-7. input capture registers (icrh, icrl)
august 28, 1998 general release specification mc68hc705jb2 programmable timer motorola rev 1.1 9-7 software can use the output compare register to measure time periods, to generate timing delays, or to generate a pulse of speci? duration or a pulse train of speci? frequency and duty cycle. writing to the ocrh before writing to the ocrl inhibits timer compares until the ocrl is written. reading or writing to the ocrl after reading the tsr will clear the output compare ?g bit (ocf). figure 9-8. timer output compare block diagram to prevent ocf from being set between the time it is read and the time the output compare registers are updated, use the following procedure: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ocrh r ocrh7 ocrh6 ocrh5 ocrh4 ocrh3 ocrh2 ocrh1 ocrh0 $0016 w reset: uuuuuuuu ocrl r ocrl7 ocrl6 ocrl5 ocrl4 ocrl3 ocrl2 ocrl1 ocrl0 $0017 w reset: uuuuuuuu u = unaffected by reset figure 9-9. output compare registers (ocrh, ocrl) ocie ocrh ($0016) 16-bit counter ? 4 internal (f osc ? 2) timer control reg. timer request output compare reset clock interrupt ocrl ($0017) ocf timer status reg. $0012 $0013 internal ($fffc) data r/w ocrh r/w ocrl bus 16-bit comparator (ocf)
general release specification august 28, 1998 motorola programmable timer mc68hc705jb2 9-8 rev 1.1 1. disable interrupts by setting the i bit in the condition code register. 2. write to the ocrh. compares are now inhibited until ocrl is written. 3. read the tsr to arm the ocf for clearing. 4. enable the output compare registers by writing to the ocrl. this also clears the ocf ?g bit in the tsr. 5. enable interrupts by clearing the i bit in the condition code register. a software example of this procedure is shown below. 9.5 timer control register (tcr) the timer control register is shown in figure 9-10 performs the following functions: enables input capture interrupts enables output compare interrupts enables timer over?w interrupts control the active edge polarity of the tcap signal on pin pb0/tcap reset clears all the bits in the tcr with the exception of the iedg bit which is unaffected. icie - input capture interrupt enable this read/write bit enables interrupts caused by an active signal on the pb0/ tcap pin. reset clears the icie bit. 1 = input capture interrupts enabled. 0 = input capture interrupts disabled. 9b ... ... b7 b6 bf ... ... 9a 16 13 17 sei ... ... sta lda stx ... ... cli ocrh tsr ocrl disable interrupts ..... ..... inhibit output compare arm ocf flag for clearing ready for next compare, ocf cleared ..... ..... enable interrupts bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcr r icie ocie toie 000 iedg 0 $0012 w reset: 000000 unaffected 0 figure 9-10. timer control register (tcr)
august 28, 1998 general release specification mc68hc705jb2 programmable timer motorola rev 1.1 9-9 ocie - output compare interrupt enable this read/write bit enables interrupts caused by a successful compare between the timer counter and the output compare registers. reset clears the ocie bit. 1 = output compare interrupts enabled. 0 = output compare interrupts disabled. toie - timer overflow interrupt enable this read/write bit enables interrupts caused by a timer over?w. reset clears the toie bit. 1 = timer over?w interrupts enabled. 0 = timer over?w interrupts disabled. iedg - input capture edge select the state of this read/write bit determines whether a positive or negative transition on the tcap pin triggers a transfer of the contents of the timer register to the input capture register. reset has no effect on the iedg bit. 1 = positive edge (low to high transition) triggers input capture. 0 = negative edge (high to low transition) triggers input capture. 9.6 timer status register (tsr) the timer status register (tsr) shown in figure 9-11 contains ?gs for the following events: an active signal on the pb0/tcap pin, transferring the contents of the timer registers to the input capture registers. a match between the 16-bit counter and the output compare registers an over?w of the timer registers from $ffff to $0000. writing to any of the bits in the tsr has no effect. reset does not change the state of any of the ?g bits in the tsr. icf - input capture flag the icf bit is automatically set when an edge of the selected polarity occurs on the pb0/tcap pin. clear the icf bit by reading the timer status register with the icf set, and then reading the low byte (icrl, $0015) of the input capture registers. reset has no effect on icf. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tsrricfocftof00000 $0013 w reset: u u u 00000 u = unaffected by reset figure 9-11. timer status registers (tsr)
general release specification august 28, 1998 motorola programmable timer mc68hc705jb2 9-10 rev 1.1 ocf - output compare flag the ocf bit is automatically set when the value of the timer registers matches the contents of the output compare registers. clear the ocf bit by reading the timer status register with the ocf set, and then accessing the low byte (ocrl, $0017) of the output compare registers. reset has no effect on ocf. tof - timer overflow flag the tof bit is automatically set when the 16-bit timer counter rolls over from $ffff to $0000. clear the tof bit by reading the timer status register with the tof set, and then accessing the low byte (tmrl, $0019) of the timer registers. reset has no effect on tof. 9.7 timer operation during wait mode during wait mode the 16-bit timer continues to operate normally and may generate an interrupt to trigger the mcu out of the wait mode. 9.8 timer operation during stop mode when the mcu enters the stop mode the free-running counter stops counting (the internal processor clock is stopped). it remains at that particular count value until the stop mode is exited by applying a low signal to the irq pin, at which time the counter resumes from its stopped value as if nothing had happened. if stop mode is exited via an external reset (logic low applied to the reset pin) the counter is forced to $fffc. if a valid input capture edge occurs at the pb0/tcap pin during the stop mode the input capture detect circuitry will be armed. this action does not set any ?gs or ?ake up the mcu, but when the mcu does ?ake up there will be an active input capture ?g (and data) from the ?st valid edge. if the stop mode is exited by an external reset, no input capture ?g or data will be present even if a valid input capture edge was detected during the stop mode.
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-1 section 10 universal serial bus module this usb module is designed for usb application in ls products. with minimized software effort, it can fully comply with usb ls device speci?ation. see usb speci?ation version 1.0 for the detail description of usb. 10.1 features integrated 3.3 volt regulator with 3.3v output pin integrated usb transceiver supporting low speed functions usb data control logic packet decoding/generation crc generation and checking nrzi encoding/decoding bit-stuf?g usb reset support control endpoint 0 and interrupt endpoints 1 and 2 two 8-byte transmit buffers one 8-byte receive buffer suspend and resume operations remote wake-up support usb generated interrupts transaction interrupt driven resume interrupt end of packet interrupt stall, nak, and ack handshake generation
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-2 rev 1.1 10.2 overview this section provides an overview of the universal serial bus (usb) module in the mc68hc705jb2. this usb module is designed to serve as a low-speed (ls) usb device per the universal serial bus speci?ation rev 1.0. three types of usb data transfers are supported: control, interrupt, and bulk (transmit only). endpoint 0 functions as a receive/transmit control endpoint. endpoints 1 and 2 can function as interrupt or bulk, but only in the transmit direction. a block diagram of the usb module is shown figure 10-1 . the usb module manages communications between the host and the usb function. the module is partitioned into four functional blocks. these blocks consist of a 3.3 volt regulator, a dual function transceiver, the usb control logic, and the endpoint registers. the blocks are further detailed in section 10.4 . figure 10-1. usb block diagram d+ d usb control logic transceiver rcv vpin vmin vpout vmout regulator 3.3 v out cpu bus usb registers usb upstream port
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-3 10.2.1 usb protocol figure 10-2 shows the various transaction types supported by the mc68hc705jb2 usb module. the transactions are portrayed as error free. the effect of errors in the data ?w are discussed later. figure 10-2. supported transaction types per endpoint each usb transaction is comprised of a series of packets. the mc68hc705jb2 usb module supports the packet types shown in figure 10-3 . token packets are generated by the usb host and decoded by the usb device. data and handshake packets are both decoded and generated by the usb device depending on the type of transaction. setup in out data0/1 data0 data1 ack data1 out ack out data0 ack ack data0/1 endpoint 0 transactions: control write control read no-data control endpoints 1 & 2 transactions: interrupt bulk transmit in ack key: unrelated bus traffic host generated device generated ack setup out in data0/1 data0 data1 ack data1 in ack in data0 ack ack ack setup in data0 data1 ack ack data0/1 in ack
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-4 rev 1.1 figure 10-3. supported usb packet types the following sections will give some detail on each segment used to form a complete usb transaction. 10.2.1.1 sync pattern the nrzi (see section 10.4.4.1 ) bit pattern shown in figure 10-4 is used as a synchronization pattern and is pre?ed to each packet. this pattern is equivalent to a data pattern of seven 0s followed by a 1 (0x80). figure 10-4. sync pattern the start of a packet (sop) is signaled by the originating port by driving the d+ and d- lines from the idle state (also referred to as the ? state) to the opposite logic level (also referred to as the ? state). this switch in levels represents the ?st bit of the sync ?ld. figure 10-5 shows the data signaling and voltage levels for the start of packet and the sync pattern. token packet: in out sync pid pid addr endp crc5 eop setup data packet: data 0 sync pid pid data crc5 eop data 1 0 - 8 bytes handshake packet: ack nak sync pid pid eop stall sync pattern pid0 pid1 idle nrzi data encoding
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-5 figure 10-5. sop, sync signaling and voltage levels 10.2.1.2 packet identi?r field the packet identi?r ?ld is an eight bit number comprised of the four bit packet identi?ation (pid) and its complement. the ?ld follows the sync pattern and determines the direction and type of transaction on the bus. table 10-1 shows the pid values for the supported packet types. table 10-1. supported packet identi?rs 10.2.1.3 address field (addr) the address ?ld is a seven bit number that is used to select a particular usb device. this ?ld is compared to the lower seven bits of the uaddr register to determine if a given transaction is targeting the mc68hc705jb2 usb device. pid value pid type %1001 in token %0001 out token %1101 setup token %0011 data0 packet %1011 data1 packet %0010 ack handshake %1010 nak handshake %1110 stall handshake end of sync first bit of packet sop bus idle v oh (min) v se (max) v se (min) v ol (min) v ss
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-6 rev 1.1 10.2.1.4 endpoint field (endp) the endpoint ?ld is a four bit number that is used to select a particular endpoint within a usb device. for the mc68hc705jb2, this will be a binary number between zero and two inclusive. any other value will cause the transaction to be ignored. 10.2.1.5 cyclic redundancy check (crc) cyclic redundancy checks are used to verify the address and data stream of a usb transaction. this ?ld is ?e bits wide for token packets and sixteen bits wide for data packets. crcs are generated in the transmitter and sent on the usb data lines after both the endpoint ?ld and the data ?ld. figure 10-6 shows how the ?e bit crc value is calculated from the data stream and veri?d for the address and endpoint ?lds of a token packet. figure 10-7 shows how the sixteen bit crc value is calculated and either transmitted or veri?d for the data packet of a given transaction. figure 10-6. crc block diagram for address and endpoint fields 00101 01100 0 5 5 5 5 next bit data stream update every bit time reset to ones at sop equal? good crc bad crc 5 yn expected residual: generator polynomial: mux 1 0
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-7 figure 10-7. crc block diagram for data packets 10.2.1.6 end of packet (eop) the single-ended 0 (se0) state is used to signal an end of packet (eop). the single-ended 0 state is indicated by both d+ and d- being below 0.8 v. eop will be signaled by driving d+ and d- to the single-ended 0 state for two bit times followed by driving the lines to the idle state for one bit time. the transition from the single- ended 0 to the idle state de?es the end of the packet. the idle state is asserted for one bit time and then both the d+ and d- output drivers are placed in their high-impedance state. the bus termination resistors hold the bus in the idle state. figure 10-8 shows the data signaling and voltage levels for an end of packet transaction. mux 0 16 16 16 16 1 0 next bit input / output update every bit time reset to ones at sop equal? good crc bad crc 16 y n expected residual: generator polynomial: data stream output data stream crc16 transmitted msb first after final data byte. transmit receive 00000 10000 0001 0 1 00000 10000 00110 1
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-8 rev 1.1 figure 10-8. eop transaction voltage levels the width of the se0 in the eop is about two bit times. the eop width is measured with the same capacitive load used for maximum rise and fall times and is measured at the same level as the differential signal crossover points of the data lines. figure 10-9. eop width timing 10.2.2 reset signaling a reset is signaled on the bus by the presence of an extended se0 at the usb data pins of a device. the reset signaling is speci?d to be present for a minimum of 10 ms. an active device (powered and not in the suspend state) seeing a single-ended zero on its usb data inputs for more than 2.5 m s may treat that signal as a reset, but must have interpreted the signaling as a reset within 5.5 m s. for a low speed device, an se0 condition between 4 and 8 low speed bit times represents a valid usb reset. a usb sourced reset will hold the mc68hc705jb2 in reset for the duration of the reset on the usb bus. the rstf bit in the usb interrupt register 0 (uir0) will be set after the internal reset is removed (see section 10.5.2 for more detail). bus driven to last bit of bus idle eop strobe packet idle state bus floats v oh (min) v se (max) v se (min) v ol (min) v ss eop width t period differential data lines data crossover level
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-9 after a reset is removed, the device will be in the attached, but not yet addressed or con?ured state (refer to section 9.1 of the usb speci?ation). the device must be able to accept a device address via a set_address command (refer to section 9.4 of the usb speci?ation) no later than 10 ms after the reset is removed. reset can wake a device from the suspended mode. a device may take up to 10ms to wake up from the suspended state. 10.2.3 suspend the mc68hc705jb2 supports suspend mode for low power. suspend mode should be entered when the usb data lines are in the idle state for more than 3.0 ms. entry into suspend mode is controlled by the suspnd bit in the usb interrupt register. any low speed bus activity should keep the device out of the suspend state. low speed devices are kept awake by periodic low speed eop signals from the host. this is referred to as low speed keep alive (refer to section 11.2.5.1 of the usb speci?ation). firmware should monitor the eopf ?g and enter suspend mode by setting the suspnd bit if an eop is not detected for 3 ms. per the usb speci?ation, the mc68hc705jb2 is required to draw less than 500 m a from the v dd supply when in the suspend state. this includes the current supplied by the voltage regulator to the 15 k w to ground termination resistors placed at the host end of the usb bus. this low current requirement means that ?mware is responsible for entering stop mode once the usb module has been placed in the suspend state. 10.2.4 resume after suspend the mc68hc705jb2 can be activated from the suspend state by normal bus activity, a usb reset signal, or by a forced resume driven from the mc68hc705jb2. 10.2.4.1 host initiated resume the host signals resume by initiating resume signalling (? state) for at least 20 ms followed by a standard low speed eop signal. this 20 ms ensures that all devices in the usb network are awakened. after resuming the bus, the host must begin sending bus traf? within 3 ms to prevent the device from re-entering suspend mode.
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-10 rev 1.1 10.2.4.2 usb reset signalling reset can wake a device from the suspended mode. a device may take up to 10 ms to wake up from the suspended state. 10.2.4.3 remote wake-up the mc68hc705jb2 also supports the remote wake-up feature. the ?mware has the ability to exit suspend mode by signaling a resume state to the upstream host or hub. a non-idle state (? state) on the usb data lines is accomplished by asserting the fresum bit in the ucr1 register. when using the remote wake-up capability, the ?mware must wait for at least 5 ms after the bus is in the idle state before sending the remote wake-up resume signaling. this allows the upstream devices to get into their suspend state and prepare for propagating resume signaling. the fresum bit should be asserted to cause the resume state on the usb data lines for at least 10ms, but not more than 15ms. note that the resume signalling is controlled by the fresum bit and meeting the timing speci?ations is dependent on the ?mware. when fresum is cleared by ?mware, the data lines will return to their high impedance state. refer to section 10.5.5 for more information about how the force resume (fresum) bit can be used to initiate the remote wake-up feature. 10.2.5 low speed device externally, low speed devices are con?ured by the position of a pull-up resistor on the usb d- pin of the mc68hc705jb2. low speed devices are terminated as shown in figure 10-10 with the pull-up on the d- line. figure 10-10. external low speed device con?uration for low speed transmissions, the transmitters eop width must be between 1.25 m s and 1.50 m s. these ranges include timing variations due to differential buffer delay and rise/fall time mismatches and to noise and other random effects. a low speed receiver must accept a 670 ns wide se0 followed by a j transition as a valid eop. an se0 narrower than 330 ns or an se0 not followed by a j transition must be rejected as an eop. an eop between 330ns and 670ns may be rejected or accepted as above. any se0 that is 2.5 m s or wider is automatically a reset. 68hc705jb2 1.5k w d+ d 3.3v regulator out usb low speed cable
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-11 10.3 clock requirements the low speed data rate is nominally 1.5 mbs. the oscxclk signal driven by the oscillator circuits is the clock source for the usb module and requires that a 6 mhz oscillator circuit be connected to the osc1 and osc2 pins. the permitted frequency tolerance for low speed functions is approximately 1.5% (15000 ppm). this tolerance includes inaccuracies from all sources: initial frequency accuracy, crystal capacitive loading, supply voltage on the oscillator, temperature, and aging. the jitter in the low speed data rate must be less than 10 ns. this tolerance allows the use of resonators in low cost, low speed devices. 10.4 hardware description the usb module as previously shown in figure 10-1 contains four functional blocks: a 3.3 volt regulator, a ls usb transceiver, the usb control logic, and the usb registers. the following will detail the function of the regulator, transceiver and control logic. see section 10.5 for the register discussion. 10.4.1 voltage regulator the usb data lines are required by the usb speci?ation to have a maximum output voltage between 2.8v and 3.6v. the data lines are also required to have an external 1.5k w pullup resistor connected between a data line and a voltage source between 3.0v and 3.6v. since the power provided by the usb cable is speci?d to be between 4.4v and 5.0v, an on-chip regulator is used to drop the voltage to the appropriate level for sourcing the usb transceiver and external pullup resistor. an output pin driven by the regulator voltage is provided to source the 1.5k w external resistor. figure 10-11 shows the worst case electrical connection for the voltage regulator. figure 10-11. regulator electrical connections ls transceiver 3.3v r2 r2 r1 r1 = 1.5k w 5% r2 = 15k w 5% regulator usb data lines host or hub usb cable 4.4v
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-12 rev 1.1 10.4.2 usb transceiver the usb transceiver provides the physical interface to the usb d+ and d- data lines. the transceiver is composed of two parts: an output drive circuit and a differential receiver. 10.4.2.1 output driver characteristics the usb transceiver uses a differential output driver to drive the usb data signal onto the usb cable. the static output swing of the driver in its low state is below the v ol of 0.3 v with a 1.5 k w load to 3.6 v and in its high state is above the v oh of 2.8 v with a 15 k w load to ground. the output swings between the differential high and low state are well balanced to minimize signal skew. slew rate control on the driver is used to minimize the radiated noise and cross talk. the drivers outputs support three-state operation to achieve bi-directional half duplex operation. the driver can tolerate a voltage on the signal pins of -0.5 v to 3.8 v with respect to local ground reference without damage. 10.4.2.2 low speed (1.5 mbs) driver characteristics the rise and fall time of the signals on this cable are greater than 75 ns to keep rfi emissions under fcc class b limits, and less than 300 ns to limit timing delays and signaling skews and distortions. the driver reaches the speci?d static signal levels with smooth rise and fall times, and minimal re?ctions and ringing when driving the cable. this driver is used only on network segments between low speed devices and the ports to which they are connected. figure 10-12. low speed driver signal waveforms one bit time (1.5 mb/s) signal pins pass output spec levels with minimal reflections and ringing v se (min) v se (max) v ss
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-13 10.4.3 receiver characteristics usb data transmission is done with differential signals. a differential input receiver is used to accept the usb data signal. a differential 1 on the bus is represented by d+ being at least 200 mv more positive than d- as seen at the receiver, and a differential 0 is represented by d- being at least 200 mv more positive than d+ as seen at the receiver. the signal cross over point must be between 1.3v and 2.0v. the receiver features an input sensitivity of 200 mv when both differential data inputs are in the range of 0.8 v to 2.5 v with respect to the local ground reference. this is called the common mode input voltage range. proper data reception is also achieved when the differential data lines are outside the common mode range, as shown in figure 10-13 . the receiver can tolerate static input voltages between ?.5v to 3.8 v with respect to its local ground reference without damage. in addition to the differential receiver, there is a single-ended receiver (schmitt trigger) for each of the two data lines. figure 10-13. differential input sensitivity over entire common mode range 10.4.3.1 receiver data jitter the data receivers for all types of devices must be able to properly decode the differential data in the presence of jitter. the more of the bit cell that any data edge can occupy and still be decoded, the more reliable the data transfer will be. data receivers are required to decode differential data transitions that occur in a window plus and minus a nominal quarter bit cell from the nominal (centered) data edge position. jitter will be caused by the delay mismatches and by mismatches in the source and destination data rates (frequencies). the receive data jitter budget for low speed is given in the electrical section of the this speci?ation. the speci?ation includes the consecutive (next) and paired transition values for each source of jitter. common mode input voltage (volts) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 1.0 0.8 0.6 0.4 0.2 minimum differential sensitivity (volts) 0
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-14 rev 1.1 10.4.3.2 data source jitter the source of data can have some variation (jitter) in the timing of edges of the data transmitted. the time between any set of data transitions is n * t period jitter time, where ? is the number of bits between the transitions and t period is de?ed as the actual period of the data rate. the data jitter is measured with the same capacitive load used for maximum rise and fall times and is measured at the crossover points of the data lines as shown in figure 10-14 . figure 10-14. data jitter for low speed transmissions, the jitter time for any consecutive differential data transitions must be within 25 ns and within 10 ns for any set of paired differential data transitions. these jitter numbers include timing variations due to differential buffer delay, rise/fall time mismatches, internal clock source jitter, and to noise and other random effects. 10.4.3.3 data signal rise and fall time the output rise time and fall time are measured between 10% and 90% of the signal. edge transition time for the rising and falling edges of low speed signals is 75 ns (minimum) into a capacitive load (c l ) of 50 pf and 300 ns (maximum) into a capacitive load of 350 pf. the rising and falling edges should be smooth transitional (monotonic) when driving the cable to avoid excessive emi. figure 10-15. data signal rise and fall time consecutive transitions t period differential data lines crossover points paired transitions t r differential data lines t f rise time fall time 10% 90% 90% 10% low speed: 75 ns at c l = 50 pf, 300 ns at c l = 350 pf c l c l
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-15 10.4.4 usb control logic the usb control logic manages data movement between the cpu and the transceiver. the control logic handles both transmit and receive operations on the usb. it contains the logic used to manipulate the transceiver and the endpoint registers. the logic contains byte count buffers for transmit operations that load the active transmit endpoints byte count and use this to determine the number of bytes to transfer. this same buffer is used for receive transactions to count the number of bytes received and, upon the end of the transaction, transfer that number to the receive endpoints byte count register. when transmitting, the control logic handles parallel to serial conversion, crc generation, nrzi encoding, and bit stuf?g. when receiving, the control logic handles sync detection, packet identi?ation, end of packet detection, bit (un)stuf?g, nrzi decoding, crc validation, and serial to parallel conversion. errors detected by the control logic include bad crc, time-out while waiting for eop, and bit stuf?g violations. 10.4.4.1 data encoding/decoding the usb employs nrzi data encoding when transmitting packets. in nrzi encoding, a 1 is represented by no change in level and a 0 is represented by a change in level. figure 10-16 shows a data stream and the nrzi equivalent and figure 10-17 is a ?w diagram for nrzi. the high level represents the j state on the data lines in this and subsequent ?ures showing nrzi encoding. a string of zeros causes the nrzi data to toggle each bit time. a string of ones causes long periods with no transitions in the data. 10.4.4.2 bit stuf?g in order to ensure adequate signal transitions, bit stuf?g is employed by the transmitting device when sending a packet on the usb (see figure 10-18 and figure 10-19 ). a 0 is inserted after every six consecutive 1s in the data stream before the data is nrzi encoded to force a transition in the nrzi data stream. this gives the receiver logic a data transition at least once every seven bit times to guarantee the data and clock lock. the receiver must decode the nrzi data, recognize the stuffed bits, and discard them. bit stuf?g is enabled beginning with the sync pattern and throughout the entire transmission. the data ?ne that ends the sync pattern is counted as the ?st one in a sequence. bit stuf?g is always enforced, without exception. if required by the bit stuf?g rules, a zero bit will be inserted even if it is the last bit before the end-of-packet (eop) signal.
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-16 rev 1.1 figure 10-16. nrzi data encoding figure 10-17. flow diagram for nrzi figure 10-18. bit stuf?g idle data idle nrzi 0110 0 000 00 0 11 1 11 power up no packet transmission idle begin packet fetch the data bit no yes no data transition transition is package transfer done? no yes data transmission is data bit = 0? idle nrzi encoded data bit stuffed data raw data stuffed bit sync pattern packet data packet data sync pattern packet data sync pattern six ones
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-17 figure 10-19. flow diagram for bit stuf?g power up no packet transmission idle no yes is package transfer done? no yes reset the bit counter to 0 insert a zero bit counter = 6? increment the counter = 0 = 1 bit value? get next bit reset bit counter to 0 begin packet transmission
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-18 rev 1.1 10.5 i/o register description the usb endpoint registers are comprised of a set of control/status registers and twenty-four data registers that provide storage for the buffering of data between the usb and the cpu. these registers are shown in table 10-2 . table 10-2. register summary register name bit 7 6 5 4 3 2 1 bit 0 addr usb control register 2 (ucr2) 0 tx1st 0 enable2 enable1 stall2 stall1 $0037 tx1str usb address register (uaddr) usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 $0038 usb interrupt register 0 (uir0) txd0f rxd0f rstf suspnd txd0ie rxd0ie 00 $0039 txd0fr rxd0fr usb interrupt register 1 (uir1) txd1f eopf resumf 0 txd1ie eopie 00 $003a resumfr txd1fr eopfr usb control register 0 (ucr0) t0seq stall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 $003b usb control register 1 (ucr1) t1seq endadd tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 $003c usb status register (usr) rseq setup 0 0 rpsiz3 rpsiz2 rpsiz1 rpsiz0 $003d usb endpoint 0 data register 0 (ue0d0) ue0rd7 ue0rd6 ue0rd5 ue0rd4 ue0rd3 ue0rd2 ue0rd1 ue0rd0 $0020 ue0td7 ue0td6 ue0td5 ue0td4 ue0td3 ue0td2 ue0td1 ue0td0 usb endpoint 0 data register 7 (ue0d7) ue0rd7 ue0rd6 ue0rd5 ue0rd4 ue0rd3 ue0rd2 ue0rd1 ue0rd0 $0027 ue0td7 ue0td6 ue0td5 ue0td4 ue0td3 ue0td2 ue0td1 ue0td0 usb endpoint 1/2 data register 0 (ue1d0) $0028 ue1td7 ue1td6 ue1td5 ue1td4 ue1td3 ue1td2 ue1td1 ue1td0 usb endpoint 1/2 data register 7 (ue1d7) $002f ue1td7 ue1td6 ue1td5 ue1td4 ue1td3 ue1td2 ue1td1 ue1td0 = unimplemented
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-19 10.5.1 usb address register (uaddr) usben ?usb module enable this read/write bit enables and disables the usb module and the usb pins. when usben is clear, the usb module will not respond to any tokens. reset clears this bit. 1 = usb function enabled 0 = usb function disabled uadd6-uadd0 ?usb function address these bits specify the usb address of the device. reset clears these bits. 10.5.2 usb interrupt register 0 (uir0) txd0f ?endpoint 0 data transmit flag this read only bit is set after the data stored in endpoint 0 transmit buffers has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this ?g by writing a logic 1 to the txd0fr bit. to enable the next data packet transmission, tx0e must also be set. if txd0f bit is not cleared, a nak handshake will be returned in the next in transaction. reset clears this bit. writing a logic 0 to txd0f has no effect. 1 = transmit on endpoint 0 has occurred 0 = transmit on endpoint 0 has not occurred rxd0f ?endpoint 0 data receive flag this read only bit is set after the usb module has received a data packet and responded with an ack handshake packet. software must clear this ?g by writing a logic 1 to the rxd0fr bit after all of the received data has been read. software must also set rx0e bit to one to enable the next data packet reception. if rxd0f bit is not cleared, a nak handshake will be returned in the next out transaction. reset clears this bit. writing a logic 0 to rxd0f has no effect. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uaddr r usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 $0038 w reset t 00000000 figure 10-20. usb address register (uaddr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uir0 r txd0f rxd0f rstf suspnd txd0ie rxd0ie 00 $0039 w txd0fr rxd0fr reset t 00000000 = unimplemented figure 10-21. usb interrupt register 0 (uir0)
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-20 rev 1.1 1 = receive on endpoint 0 has occurred 0 = receive on endpoint 0 has not occurred rstf ?usb reset flag this read only bit is set when a valid reset signal state is detected on the d+ and d- lines. this reset detection will also generate an internal reset signal to reset the cpu and other peripherals including the usb module. this bit is cleared by writing a logic 1 to the rstfr bit in the ucr2 register. this bit is cleared by a por reset. suspnd ?usb suspend flag to save power, this read/write bit should be set by the software if a 3ms constant idle state is detected on usb bus. setting this bit stops the clock to the usb and causes the usb module to enter suspend mode. unnecessary analog circuitry will be powered down. software must clear this bit after the resume ?g (resumf) is set while this resume interrupt ?g is serviced. txd0ie ?endpoint 0 transmit interrupt enable this read/write bit enables the transmit endpoint 0 to generate a usb interrupt when the txd0f bit becomes set. 1 = usb interrupts enabled for transmit endpoint 0 0 = usb interrupts disabled for transmit endpoint 0 rxd0ie ?endpoint 0 receive interrupt enable this read/write bit enables the transmit endpoint 0 to generate a usb interrupt when the rxd0f bit becomes set. 1 = usb interrupts enabled for receive endpoint 0 0 = usb interrupts disabled for receive endpoint 0 txd0fr ?endpoint 0 transmit flag reset writing a logic 1 to this write only bit will clear the txd0f bit if it is set.writing a logic 0 to txd0fr has no effect. reset clears this bit. rxd0fr ?endpoint 0 receive flag reset writing a logic 1 to this write only bit will clear the rxd0f bit if it is set.writing a logic 0 to rxd0fr has no effect. reset clears this bit. 10.5.3 usb interrupt register 1 (uir1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uir1 r txd1f eopf resumf 0 txd1ie eopie 00 $003a w resumfr txd1fr eopfr reset t 00000000 = unimplemented figure 10-22. usb interrupt register 1(uir1)
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-21 txd1f ?endpoint 1/endpoint 2 data transmit flag this read only bit is shared by endpoint 1 and endpoint 2. it is set after the data stored in the shared endpoint 1/endpoint 2 transmit buffer has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this ?g by writing a logic 1 to the txd1fr bit. to enable the next data packet transmission, tx1e must also be set. if txd1f bit is not cleared, a nak handshake will be returned in the next in transaction. reset clears this bit. writing a logic 0 to txd1f has no effect. 1 = transmit on endpoint 1 or endpoint 2 has occurred 0 = transmit on endpoint 1 or endpoint 2 has not occurred eopf ?end of packet detect flag this read only bit is set when a valid end-of-packet sequence is detected on the d+ and d- lines. software must clear this ?g by writing a logic 1 to the eopfr bit. reset clears this bit. writing a logic 0 to eopf has no effect. 1 = end-of-packet sequence has been detected 0 = end-of-packet sequence has not been detected resumf ?resume flag this read only bit is set when usb bus activity is detected while the suspnd bit is set. software must clear this ?g by writing a logic 1 to the resumfr bit. reset clears this bit. writing a logic 0 to resumf has no effect. 1 = usb bus activity has been detected 0 = no usb bus activity has been detected resumfr ?resume flag reset writing a logic 1 to this write only bit will clear the resumf bit if it is set. writing a logic 0 to resumfr has no effect. reset clears this bit. txd1ie ?endpoint 1/endpoint 2 transmit interrupt enable this read/write bit enables the usb to generate an interrupt when the shared transmit endpoint 1/endpoint 2 interrupt ?g (txd1f) bit becomes set. reset clears this bit. 1 = usb interrupts enabled for transmit endpoints 1 and 2 0 = usb interrupts disabled for transmit endpoints 1 and 2 eopie ?end of packet detect interrupt enable this read/write bit enables the usb to generate an interrupt when the eopf bit becomes set. reset clears this bit. 1 = usb interrupts enabled for transmit endpoints 1 and 2 0 = usb interrupts disabled for transmit endpoint 1 and 2 txd1fr ?endpoint 1/endpoint 2 transmit flag reset writing a logic 1 to this write only bit will clear the txd1f bit if it is set. writing a logic 0 to txd1fr has no effect. reset clears this bit.
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-22 rev 1.1 eopfr ?end of packet flag reset writing a logic 1 to this write only bit will clear the eopf bit if it is set. writing a logic 0 to the eopfr has no effect. reset clears this bit. 10.5.4 usb control register 0 (ucr0) t0seq ?endpoint 0 transmit sequence bit this read/write bit determines which type of data packet (data0 or data1) will be sent during the next in transaction. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active for next endpoint 0 transmit 0 = data0 token active for next endpoint 0 transmit stall0 ?endpoint 0 force stall bit this read/write bit causes endpoint 0 to return a stall handshake when polled by either an in or out token by the usb host controller. the usb hardware clears this bit when a setup token is received. reset clears this bit. 1 = send stall handshake 0 = default tx0e ?endpoint 0 transmit enable this read/write bit enables a transmit to occur when the usb host controller sends an in token to endpoint 0. software should set this bit when data is ready to be transmitted. it must be cleared by software when no more endpoint 0 data needs to be transmitted. if this bit is 0 or the txd0f is set, the usb will respond with a nak handshake to any endpoint 0 in tokens. reset clears this bit. 1 = data is ready to be sent. 0 = data is not ready. respond with nak. rx0e ?endpoint 0 receive enable this read/write bit enables a receive to occur when the usb host controller sends an out token to endpoint 0. software should set this bit when data is ready to be received. it must be cleared by software when data cannot be received. if this bit is 0 or the rxd0f is set, the usb will respond with a nak handshake to any endpoint 0 out tokens. reset clears this bit. 1 = data is ready to be received. 0 = not ready for data. respond with nak. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ucr0 r t0seq stall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 $003b w reset t 00000000 figure 10-23. usb control register 0 (ucr0)
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-23 tp0siz3-tp0siz0 ?endpoint 0 transmit data packet size these read/write bits store the number of transmit data bytes for the next in token request for endpoint 0. these bits are cleared by reset. 10.5.5 usb control register 1 (ucr1) t1seq ?endpoint1/endpoint 2 transmit sequence bit this read/write bit determines which type of data packet (data0 or data1) will be sent during the next in transaction directed to endpoint 1 or endpoint 2. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active for next endpoint 1/endpoint 2 transmit 0 = data0 token active for next endpoint 1/endpoint 2 transmit endadd ?endpoint address select this read/write bit speci?s whether the data inside the registers ue1d0- ue1d7 are used for endpoint 1 or endpoint 2. if all the conditions for a successful endpoint 2 usb response to a hosts in token are satis?d (txd1f=0, tx1e=1, stall2=0, and enable2=1) except that the endadd bit is con?ured for endpoint 1, the usb responds with a nak handshake packet. 1 = the data buffers are used for endpoint 2 0 = the data buffers are used for endpoint 1 tx1e ?endpoint 1/endpoint 2 transmit enable this read/write bit enables a transmit to occur when the usb host controller sends an in token to endpoint 1 or endpoint 2. the appropriate endpoint enable bit, enable1 or enable2 bit in the ucr2 register, should also be set. software should set the tx1e bit when data is ready to be transmitted. it must be cleared by software when no more data needs to be transmitted. if this bit is 0 or the txd1f is set, the usb will respond with a nak handshake to any endpoint 1 or endpoint 2 directed in tokens. reset clears this bit. 1 = data is ready to be sent. 0 = data is not ready. respond with nak. fresum ?force resume this read/write bit forces a resume state (? or non-idle state) onto the usb data lines to initiate a remote wake-up. software should control the timing of the forced resume to be between 10ms and 15 ms. setting this bit will not cause the resumf bit to set. 1 = force data lines to ? state 0 = default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ucr1 r t1seq endadd tx1e fresum tp1sz3 tp1siz2 tp1siz1 tp1siz0 $003c w reset t 00000000 figure 10-24. usb control register 1 (ucr1)
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-24 rev 1.1 tp1siz3-tp1siz0 ?endpoint 1/endpoint 2 transmit data packet size these read/write bits store the number of transmit data bytes for the next in token request for endpoint 1 or endpoint 2. these bits are cleared by reset. 10.5.6 usb control register 2 (ucr2) tx1str ?clear transmit first flag writing a logic 1 to this write-only bit will clear the tx1st bit if it is set. writing a logic 0 to the tx1str has no effect. reset clears this bit. tx1st ?transmit first flag this read-only bit is set if the endpoint 0 data transmit flag (txd0f) is set when the usb control logic is setting the endpoint 0 data receive flag (rxd0f). that is, this bit will be set if an endpoint 0 transmit flag is still set at the end of an endpoint 0 reception. this bit lets the ?mware know that the endpoint 0 transmission happened before the endpoint 0 reception. reset clears this bit. 1 = in transaction occurred before setup/out. 0 = in transaction occurred after setup/out. enable2 ?endpoint 2 enable this read/write bit enables endpoint 2 and allows the usb to respond to in packets addressed to endpoint 2. reset clears this bit. 1 = endpoint 2 is enabled and can respond to an in token. 0 = endpoint 2 is disabled enable1 ?endpoint 1 enable this read/write bit enables endpoint 1 and allows the usb to respond to in packets addressed to endpoint 1. reset clears this bit. 1 = endpoint 1 is enabled and can respond to an in token. 0 = endpoint 1 is disabled stall2 ?endpoint 2 force stall bit this read/write bit causes endpoint 2 to return a stall handshake when polled by either an in or out token by the usb host controller. reset clears this bit. 1 = send stall handshake. 0 = default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ucr2 r 0 tx1st 0 enable2 enable1 stall2 stall1 $0037 w tx1str reset t - - 0 - 0000 = unimplemented figure 10-25. usb control register 2 (ucr2)
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-25 stall1 ?endpoint 1 force stall bit this read/write bit causes endpoint 1 to return a stall handshake when polled by either an in or out token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default 10.5.7 usb status register (usr) rseq ?endpoint 0 receive sequence bit this read only bit indicates the type of data packet last received for endpoint 0 (data0 or data1). 1 = data1 token received in last endpoint 0 receive 0 = data0 token received in last endpoint 0 receive setup ?setup token detect bit this read only bit indicates that a valid setup token has been received. 1 = last token received for endpoint 0 was a setup token 0 = last token received for endpoint 0 was not a setup token rpsiz3-rpsiz0 ?endpoint 0 receive data packet size these read only bits store the number of data bytes received for the last out or setup transaction for endpoint 0. these bits are not affected by reset. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 usr r rseq setup 0 0 rpsiz3 rpsiz2 rpsiz1 rpsiz0 $003d w reset t uuuuuuuu = unimplemented figure 10-26. usb status register (usr)
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-26 rev 1.1 10.5.8 usb endpoint 0 data registers (ue0d0-ue0d7) ue0rd7 - ue0rd0 ?endpoint 0 receive data buffer these read only bits are serially loaded with out token or setup token data received over the usbs d+ and d- pins. ue0td7 - ue0td0 ?endpoint 0 transmit data buffer these write only buffers are loaded by software with data to be sent on the usb bus on the next in token directed at endpoint 0. 10.5.9 usb endpoint 1/endpoint 2 data registers (ue1d0-ue1d7) ue1td7 - ue1td0 ?endpoint 1/ endpoint 2 transmit data buffer these write only buffers are loaded by software with data to be sent on the usb bus on the next in token directed at endpoint 1 or endpoint 2. these buffers are shared by endpoints 1 and 2 and depend on proper con?uration of the endadd bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue0d0 r ue0rd7 ue0rd6 ue0rd5 ue0rd4 ue0rd3 ue0rd2 ue0rd1 ue0rd0 $0020 w ue0td7 ue0td6 ue0td5 ue0td4 ue0td3 ue0td2 ue0td1 ue0td0 to :::::::: :::::::: ue0d7 r ue0rd7 ue0rd6 ue0rd5 ue0rd4 ue0rd3 ue0rd2 ue0rd1 ue0rd0 $0027 w ue0td7 ue0td6 ue0td5 ue0td4 ue0td3 ue0td2 ue0td1 ue0td0 reset t xxxxxxxx figure 10-27. usb endpoint 0 data register (ue0d0-ue0d7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ue1d0 r $0028 w ue1td7 ue1td6 ue1td5 ue1td4 ue1td3 ue1td2 ue1td1 ue1td0 to :::::::: :::::::: ue1d7 r $002f w ue1td7 ue1td6 ue1td5 ue1td4 ue1td3 ue1td2 ue1td1 ue1td0 reset t xxxxxxxx figure 10-28. usb endpoint 1/endpoint2 data registers (ue1d0-ue1d7)
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-27 10.6 usb interrupts the usb module is capable of generating interrupts and causing the cpu to execute the usb interrupt service routine. there are three types of usb interrupts: end of transaction interrupts signify a completed transaction (receive or transmit) resume interrupts signify that the usb bus is reactivated after having been suspended end of packet interrupts signify that a low speed end of packet signal was detected all usb interrupts share the same interrupt vector. firmware is responsible for determining which interrupt is active. 10.6.1 usb end of transaction interrupt there are three possible end of transaction interrupts: endpoint 0 receive, endpoint 0 transmit, and a shared endpoint 1 or endpoint 2 transmit. end of transaction interrupts occur as detailed in the following sections. 10.6.1.1 receive control endpoint 0 for a control out transaction directed at endpoint 0, the usb module will generate an interrupt by setting the rxd0f ?g in the uir0 register. the conditions necessary for the interrupt to occur are shown in the ?wchart of figure 10-29 . setup transactions cannot be stalled by the usb function. a setup received by a control endpoint will clear the stall0 bit if it is set. the conditions for receiving a setup interrupt are shown in figure 10-30 . 10.6.1.2 transmit control endpoint 0 for a control in transaction directed at endpoint 0, the usb module will generate an interrupt by setting the txd0f ?g in the uir0 register. the conditions necessary for the interrupt to occur are shown in the ?wchart of figure 10-31 . 10.6.1.3 transmit endpoint 1 and transmit endpoint 2 transmit endpoints 1 & 2 share their interrupt ?g. for an in transaction directed at endpoint 1 or 2, the usb module will generate an interrupt by setting the txd1f ?g in the uir1 register. the conditions necessary for the interrupt to occur are shown in the ?wchart of figure 10-32 .
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-28 rev 1.1 10.6.2 resume interrupt the usb module will generate a usb interrupt if low speed bus activity is detected after entering the suspend state. a transition of the usb data lines to the non-idle state (? state) while in the suspend mode will set the resumf ?g in the uir1 register. there is no interrupt enable bit for this interrupt source and an interrupt will be executed if the i bit in the ccr is cleared. a resume interrupt can only occur while the mc68hc705jb2 is in the suspend mode. 10.6.3 end of packet interrupt the usb module can generate a usb interrupt upon detection of an end of packet signal (a single ended 0) for low speed devices. upon detection of an se0 sequence, the usb module sets the eopf bit and will generate an interrupt if the eopie bit in the uir1 register is set.
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-29 figure 10-29. out token data flow for receive endpoint 0 valid out token received for endpoint 0 endpoint 0 receive enabled? (usben = 1) endpoint 0 receive ready to receive? (rx0e = 1) && (rxd0f = 0) error free data packet? no response from usb function send nak handshake ignore transaction no response from usb function set rxd0f to 1 receive control endpoint interrupt enabled? (rxd0ie = 1) no interrupt valid transaction interrupt generated endpoint 0 receive not stalled? (stall0 = 0) send stall handshake accept data valid data token received for endpoint 0? no response from usb function time-out n n n n n n y y y y y y y set/clear rseq bit
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-30 rev 1.1 figure 10-30. setup token data flow for receive endpoint 0 valid setup token received for endpoint 0 endpoint 0 receive enabled? (usben = 1) error free data packet? no response from usb function ignore transaction no response from usb function set rxd0f to 1 receive control endpoint interrupt enabled? (rxd0ie = 1) no interrupt valid transaction interrupt generated accept data set setup to 1 n n n y y y y y y stall0 = 0? n clear stall0 bit endpoint 0 receive ready to receive? (rx0e = 1) && (rxd0f = 0) n y set/clear rseq bit no response from usb function
august 28, 1998 general release specification mc68hc705jb2 universal serial bus module motorola rev 1.1 10-31 figure 10-31. in token data flow for transmit endpoint 0 transmit endpoint enabled? (usben = 1) transmit endpoint ready to transfer? (tx0e = 1) && (txd0f = 0) no response from usb function send nak handshake ack received and no set txd0f to 1 transmit endpoint interrupt enabled? (txd0ie = 1) no interrupt valid transaction interrupt generated transmit endpoint not stalled by firmware? (stall0 = 0) send stall handshake send data data pid set by t0seq valid in token received for endpoint 0 n y n n y y y no response from usb function n y time-out condition occur? n
general release specification august 28, 1998 motorola universal serial bus module mc68hc705jb2 10-32 rev 1.1 figure 10-32. in token data flow for transmit endpoint 1/ endpoint 2 transmit endpoint enabled? (usben = 1) transmit endpoint ready to transfer? (tx1e = 1) && (txd1f = 0) & no response from usb function send nak handshake set txd1f to 1 transmit endpoint interrupt enabled? (txd1ie = 1) no interrupt valid transaction interrupt generated transmit endpoint not stalled by firmware? (stall1 & endp1) + (stall2 & endp2) send stall handshake send data data pid set by t1seq valid in token received for endpoints 1 or 2 n n n y y y ack received and no time-out condition occurs? no response from usb function n y ((endp2 & endadd) + (endp1 & endadd )) endp1 is endpoint 1 directed traffic endp2 is endpoint 2 directed traffic note:
august 28, 1998 general release specification mc68hc705jb2 eprom motorola rev 1.1 11-1 section 11 eprom this section describes erasable programmable read-only memory (eprom) programming. 11.1 eprom the on-chip user eprom consists of 2048 bytes of eprom from $1600 to $1dff and 16 bytes of user vectors from $1ff0 to $1fff. the bootloader rom and vectors are located from $1e00 to $1fef. 12 of the user vectors, $1ff4-$1fff, are dedicated to reset and interrupt vectors. the four remaining locations, $1ff0-$1ff3, are reserved for test functions. the mask option register is located at $01ff. 11.2 bootloader this program (contained in an on-chip boot rom) handles copying of user code from an external eprom into the on-chip eprom. the bootloader function does not have to be done from an eprom, but can be done from a host. 11.2.1 bootloader mode bootloader mode is entered upon the rising edge of reset if the irq /v pp pin is at v tst and the pb0 pin is at logic zero. the bootloader performs one programming pass at 1ms per byte then does a verify pass. the user code must be a one-to-one correspondence with the internal eprom addresses. table 11-1. operation mode condition after reset reset pin i rq /vpp pb0/tcap mode v ss to v dd v ss to v dd single-chip (normal) v tst v ss bootloader v tst = 2 x v dd
general release specification august 28, 1998 motorola eprom mc68hc705jb2 11-2 rev 1.1 11.3 eprom programming programming the on-chip eprom is achieved by using the program control register located at address $3e. please contact motorola for programming board availability. 11.3.1 eprom program control register (pcr) this register is provided for programming the on-chip eprom. moron ?mask option register on 0 = disable programming to mask option register ($01ff) 1 = enable programming to mask option register ($01ff) elat ?eprom latch control 0 = eprom address and data bus con?ured for normal reads 1 = eprom address and data bus con?ured for programming (writes to eprom cause address and data to be latched). eprom is in programming mode and cannot be read if elat is 1. this bit should not be set when no programming voltage is applied to the v pp pin. pgm ?eprom program command 0 = programming power is switched off from eprom array. 1 = programming power is switched on to eprom array. if elat 1 1, then pgm = 0. 11.3.2 programming sequence the eprom programming sequence is: 1. set the elat bit 2. write the data to the address to be programmed 3. set the pgm bit 4. delay for a time t pgmr 5. clear the pgm bit 6. clear the elat bit the last two steps must be performed with separate cpu writes. pcr $003e bit-7 bit-6 bit-5 bit4 bit-3 bit-2 bit1 bit-0 read reserved moron elat pgm write reset 0000 0 000
august 28, 1998 general release specification mc68hc705jb2 eprom motorola rev 1.1 11-3 caution it is important to remember that an external programming voltage must be applied to the v pp pin while programming, but it should be equal to v dd during normal operations. figure 11-1 shows the ?w required to successfully program the eprom. figure 11-1. eprom programming sequence start elat=1 write eprom byte epgm=1 wait 1ms epgm=0 elat=0 write additional byte? n y end
general release specification august 28, 1998 motorola eprom mc68hc705jb2 11-4 rev 1.1 11.4 mask option register (mor), $01ff the mask option register (mor) contains programmable eprom bits to control mask options. in order to program this register the moron bit in pcr need to be set to ? before doing the eprom programming process. irqtrig ?irq, pa0-pa3 interrupt options 1 = edge-trigger only 0 = edge-and-level-triggered pullren ?port a and b pullup/pulldown options 1 = connected 0 = disconnected painten ?pa0-pa3 external interrupt options 1 = disabled 0 = enabled oscdly ?oscillator delay option 1 = 128 internal clock cycles 0 = 4064 internal clock cycles lvren ?lvr option 1 = enabled 0 = disabled bit-7 bit-6 bit-5 bit4 bit-3 bit-2 bit1 bit-0 mor $01ff read irqtrig pullren painten oscdly lvren write erased 0001 1 111 reset unaffected
august 28, 1998 general release specification mc68hc705jb2 instruction set motorola rev 1.1 12-1 section 12 instruction set this section describes the addressing modes and instruction types. 12.1 addressing modes the cpu uses eight addressing modes for ?xibility in accessing data. the addressing modes de?e the manner in which the cpu ?ds the data required to execute an instruction. the eight addressing modes are the following: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative 12.1.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry ?g (sec) and increment accumulator (inca). inherent instructions require no memory address and are one byte long. 12.1.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no memory address and are two bytes long. the opcode is the ?st byte, and the immediate data value is the second byte.
general release specification august 28, 1998 motorola instruction set mc68hc705jb2 12-2 rev 1.1 12.1.3 direct direct instructions can access any of the ?st 256 memory addresses with two bytes. the ?st byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. brset and brclr are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. 12.1.4 extended extended instructions use only three bytes to access any address in memory. the ?st byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. 12.1.5 indexed, no offset indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the ?st 256 memory locations. the index register contains the low byte of the conditional address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000?00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 12.1.6 indexed, 8-bit offset indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the ?st 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the conditional address of the operand. these instructions can access locations $0000?01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the ?st 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.
august 28, 1998 general release specification mc68hc705jb2 instruction set motorola rev 1.1 12-3 12.1.7 indexed, 16-bit offset indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the conditional address of the operand. the ?st byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. these instructions can address any location in memory. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. 12.1.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu ?ds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, twos complement byte that gives a branching range of ?28 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and veri?s that it is within the span of the branch. 12.1.9 instruction types the mcu instructions fall into the following ?e categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions
general release specification august 28, 1998 motorola instruction set mc68hc705jb2 12-4 rev 1.1 12.1.10 register/memory instructions most of these instructions use two operands. one operand is in either the accumulator or the index register. the cpu ?ds the other operand in memory. table 12-1 lists the register/memory instructions. table 12-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub
august 28, 1998 general release specification mc68hc705jb2 instruction set motorola rev 1.1 12-5 12.1.11 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modi?d value back to the memory location or to the register. the test for negative or zero instruction (tst) is an exception to the read-modify-write sequence because it does not write a replacement value. table 12-2 lists the read-modify-write instructions. 12.1.12 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump to subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. all branch instructions use relative addressing. bit test and branch instructions cause a branch based on the state of any readable bit in the ?st 256 memory locations. these three-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu ?ds the conditional branch destination by adding the table 12-2. read-modify-write instructions instruction mnemonic arithmetic shift left asl arithmetic shift right asr clear bit in memory bclr set bit in memory bset clear clr complement (one? complement) com decrement dec increment inc logical shift left lsl logical shift right lsr negate (two? complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst
general release specification august 28, 1998 motorola instruction set mc68hc705jb2 12-6 rev 1.1 third byte to the program counter if the speci?d bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ?28 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. table 12-3 lists the jump and branch instructions. table 12-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr
august 28, 1998 general release specification mc68hc705jb2 instruction set motorola rev 1.1 12-7 12.1.13 bit manipulation instructions the cpu can set or clear any writable bit in the ?st 256 bytes of memory. port registers, port data direction registers, timer registers, and on-chip ram locations are in the ?st 256 bytes of memory. the cpu can also test and branch based on the state of any bit in any of the ?st 256 memory locations. bit manipulation instructions use direct addressing. table 12-4 lists these instructions. 12.1.14 control instructions these register reference instructions control cpu operation during program execution. control instructions, listed in table 12-5 , use inherent addressing. table 12-4. bit manipulation instructions instruction mnemonic clear bit bclr branch if bit clear brclr branch if bit set brset set bit bset table 12-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait
general release specification august 28, 1998 motorola instruction set mc68hc705jb2 12-8 rev 1.1 12.1.15 instruction set summary table 12-6 is an alphabetical list of all m68hc05 instructions and shows the effect of each instruction on the condition code register. table 12-6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles h i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ? (a) (m) imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? z = 1 rel 27 rr 3 c b0 b7 0 b0 b7 c
august 28, 1998 general release specification mc68hc705jb2 instruction set motorola rev 1.1 12-9 bhcc rel branch if half-carry bit clear pc ? (pc) + 2 + rel ? h = 0 rel 28 rr 3 bhcs rel branch if half-carry bit set pc ? (pc) + 2 + rel ? h = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? c z = 0 rel 22 rr 3 bhs rel branch if higher or same pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff p 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc ? (pc) + 2 + rel ? mn = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brset n opr rel branch if bit n set pc ? (pc) + 2 + rel ? mn = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc
general release specification august 28, 1998 motorola instruction set mc68hc705jb2 12-10 rev 1.1 bset n opr set bit n mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1 pc ? (pc) + rel rel ad rr 6 clc clear carry bit c ? 0 0 inh 98 2 cli clear interrupt mask i ? 0 0 inh 9a 2 clr opr clra clrx clr opr ,x clr ,x clear byte m ? $00 a ? $00 x ? $00 m ? $00 m ? $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ?(m) imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one? complement) m ? ( ) = $ff ?(m) a ? ( ) = $ff ?(m) x ? ( ) = $ff ?(m) m ? ( ) = $ff ?(m) m ? ( ) = $ff ?(m) 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ?(m) imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? (m) ?1 a ? (a) ?1 x ? (x) ?1 m ? (m) ?1 m ? (m) ?1 dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ? (a) ? (m) imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc m a x m m
august 28, 1998 general release specification mc68hc705jb2 instruction set motorola rev 1.1 12-11 inc opr inca incx inc opr ,x inc ,x increment byte m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n (n = 1, 2, or 3) push (pcl); sp ? (sp) ?1 push (pch); sp ? (sp) ?1 pc ? conditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ? (m) imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ? (m) imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ? (x) (a) 0 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (two? complement) m ? ?m) = $00 ?(m) a ? ?a) = $00 ?(a) x ? ?x) = $00 ?(x) m ? ?m) = $00 ?(m) m ? ?m) = $00 ?(m) dir inh inh ix1 ix 30 40 50 60 70 ii ff 5 3 3 6 5 nop no operation inh 9d 2 table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc c b0 b7 0 b0 b7 c 0
general release specification august 28, 1998 motorola instruction set mc68hc705jb2 12-12 rev 1.1 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ? (a) (m) imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ? $00ff inh 9c 2 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (a) ?(m) ?(c) imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ? 1 1 inh 99 2 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ? (a) dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin 0 inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ? (x) dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc c b0 b7 b0 b7 c
august 28, 1998 general release specification mc68hc705jb2 instruction set motorola rev 1.1 12-13 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (a) ?(m) imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1; push (x) sp ? (sp) ?1; push (a) sp ? (sp) ?1; push (ccr) sp ? (sp) ?1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 10 tax transfer accumulator to index register x ? (a) inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ?$00 dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ? (x) inh 9f 2 wait stop cpu clock and enable interrupts 0 inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ? ) negation (two? complement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag set or cleared n any bit not affected table 12-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc
motorola instruction set mc68hc705jb2 12-14 rev 1.1 table 12-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 tax 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb
august 28, 1998 general release specification mc68hc705jb2 electrical specifications motorola rev 1.1 13-1 section 13 electrical specifications 13.1 maximum ratings this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either v ss or v dd ). 13.2 thermal characteristics table 13-1. maximum ratings (voltages referenced to v ss ) rating symbol value unit supply voltage v dd 0.3 to +7.0 v input voltage v in v ss 0.3 to v dd +0.3 v eprom programming voltage v pp 15 v current drain per pin excluding pb1, pb2, v dd and v ss i ?5 ma operating temperature range (standard) (extended) t a t l to t h 0 to +70 40 to +85 c storage temperature range t stg 65 to +150 c table 13-2. thermal characteristics characteristic symbol value unit thermal resistance 20-pin pdip 20-pin soic q ja q ja 68 91 c/w c/w
general release specification august 28, 1998 motorola electrical specifications mc68hc705jb2 13-2 rev 1.1 13.3 dc electrical characteristics table 13-3. dc electrical characteristics (v dd = 4.2v to 5.5v, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted) characteristic symbol min typ max unit output voltage i load = 10.0 m a v ol v oh v dd 0.1 0.1 v output high voltage (i load =?.8 ma) pa0-5, pb0 v oh v dd 0.8 v output low voltage (i load = 1.6 ma) pa0-3, pb0 (i load = 8.0 ma) pa4-7 (i load = 25.0 ma) pb1, pb2 (note 8) v ol 0.4 0.4 0.5 v input high voltage pa0-7, pb0-2, irq , reset , osc1 v ih 0.7 v dd ? dd v input low voltage pa0-7, pb0-2, irq , reset , osc1 v il v ss 0.2 v dd v supply current (see notes) run (usb active) run (usb suspended) wait (usb active) wait (usb suspended) stop 25 c 0 c to +70 c i dd 10 2.3 8.8 1.0 200 300 12 4.0 10 2.0 250 400 ma ma ma ma m a m a i/o ports hi-z leakage current pa0-7, pb0-2 (without individual pulldown/up activated) i z 10 m a input pulldown current pa0-7, pb0 (with individual pulldown activated) i il 50 100 200 m a input current reset , irq , osc1 i in 1 m a capacitance ports (as input or output) rese t , irq , osc1, osc2 c out c in 12 8 pf pf crystal/ceramic resonator oscillator mode internal resistor osc1 to osc2 r osc 1.0 2.0 3.0 m w pullup resistor pb1, pb2 r pull-up 25 100 200 k w lvr inhibit (see note 9) v lvri 3.0 3.3 3.6 v lvr recover (see note 9) v lvrr 3.1 3.5 3.7 v
august 28, 1998 general release specification mc68hc705jb2 electrical specifications motorola rev 1.1 13-3 notes: 1. all values shown reflect average measurements. 2. typical values at midpoint of voltage range, 25 c only. 3. wait i dd : only timer system (mft) active. 4. run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 (f osc = 6.0 mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l = 20 pf on osc2. 5. wait, stop i dd : all ports configured as inputs, v il = 0.2 vdc, v ih = v dd -0.2 vdc. 6. stop i dd measured with osc1 = v ss . 7. wait i dd is affected linearly by the osc2 capacitance. 8. t a = 0 c to +40 c. 9. these are preliminary specifications. 13.4 usb dc electrical characteristics table 13-4. usb dc electrical characteristics (v dd = 4.2v to 5.5v, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted) characteristic symbol conditions min typ max unit hi-z state data line leakage i lo 0v general release specification august 28, 1998 motorola electrical specifications mc68hc705jb2 13-4 rev 1.1 13.5 usb low speed source electrical characteristics notes: 1. all voltages measured from local ground, unless otherwise specified. 2. all timings use a capacitive load of 50pf, unless otherwise specified. 3. low speed timings have a 1.5k pull-up to 2.8v on the d- data line. 4. measured from 10% to 90% of the data signal. 5. the rising and falling edges should be smooth transitional (monotonic). 6. timing differences between the differential data signals. 7. measured at crossover point of differential data signals. 8. capacitive loading includes 50pf of tester capacitance. table 13-5. usb low speed source electrical characteristics parameter symbol conditions (notes 1,2,3) min typ max unit transition time: rise time fall time t r t f notes 4, 5, 8 c l =50pf c l =350pf c l =50pf c l =350pf 75 75 300 300 ns ns ns ns rise/fall time matching t rfm t r /t f 80 120 % output signal crossover voltage v crs 1.3 2.0 v low speed data rate t drate 1.5mbs 1.5% 1.4775 676.8 1.500 666.0 1.5225 656.8 mbs ns source differential driver jitter to next transition for paired transitions t udj1 t udj2 c l =350pf notes 6,7 and figure 12-2 ?5 ?0 25 10 ns ns receiver data jitter tolerance to next transition for paired transitions t djr1 t djr2 c l =350pf notes 7 and figure 12-4 ?5 ?5 75 45 ns ns source eop width teopt note 7 and figure 12-3 1.25 1.50 m s differential to eop transition skew tdeop note 7 and figure 12-3 ?0 100 ns receiver eop width must reject as eop must accept t eopr1 t eopr2 note 7 and figure 12-3 330 675 ns ns
august 28, 1998 general release specification mc68hc705jb2 electrical specifications motorola rev 1.1 13-5 13.6 control timing 1. the minimum period t ilil or t ihih should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . 2. effects of processing, temperature, and supply voltage (excluding tolerances of external r and c) 3. t slow is a parameter dependent on f osc and loading. typical value of t slow is tentatively set at 170 ns with minimal value of 130ns and maximal value of 185ns under the simulation conditions that f osc is 6.0 mhz and slow output transition feature is enabled. capacitive loadings of 50pf on pb1-pb2, are assumed. actual transition time will be specified to replace the tbds when enough characterization has been done on various wafers from different lots. the values listed here represent data off simulati on runs under the specified conditions. under no circumstances should they be treated as the final specification. 13.7 eprom programming specifications table 13-6. control timing (v dd = 4.2v to 5.5v, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted) characteristic symbol min max units frequency of operation crystal oscillator option external clock source f osc f osc dc 6 6 mhz mhz internal operating frequency crystal oscillator (f osc ? 2) external clock (f osc ? 2) f op f op dc 3 3 mhz mhz cycle time (1/f op )t cyc 330 ns reset pulse width low t rl 1.5 t cyc irq interrupt pulse width low (edge-triggered) t ilih 0.5 t cyc irq interrupt pulse period t ilil note 1 t cyc pa0 to pa3, interrupt pulse width high (edge-triggered) t ihil 0.5 t cyc pa0 to pa3, interrupt pulse period t ihih note 1 t cyc osc1 pulse width t oh , t ol ns output high to low transition period on pb1 (note 3) t slow ns table 13-7. eprom programming electrical characteristics (v dd = 4.2v to 5.5v, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted) characteristic symbol min typ max unit programming voltage irq /v pp v pp 10 12 15 v programming current irq /v pp i pp ?ma programming time per byte t epgm 14ms
general release specification august 28, 1998 motorola electrical specifications mc68hc705jb2 13-6 rev 1.1
august 28, 1998 general release specification mc68hc705jb2 mechanical specifications motorola rev 1.1 14-1 section 14 mechanical specifications this section provides the mechanical dimensions for the two available packages for mc68hc705jb2: the 20-pin pdip and 20-pin soic. 14.1 20-pin plastic dual-in-line package (pdip) figure 14-1. 20-pin pdip mechanical dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 a seating plane k n f g d 20 pl t m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc
general release specification august 28, 1998 motorola mechanical specifications mc68hc705jb2 14-2 rev 1.1 14.2 20-pin surface-mount small outline package (soic) figure 14-2. 20-pin soic mechanical dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c t seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029

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